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For university lab, a random number generating function used "mul" instruction which isn't included with Nios II/e version, causing pc to jump to 0x20 from mul instruction. So, I tried building Nios II/s in SOPC by modifying the .sopc file found in C:\altera\91sp2\University_Program\NiosII_Computer_Systems\DE1\DE1_Basic_Computer
Now I can't load my program on the monitor program. It gives me the error: Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 Resetting and pausing target processor: OK Reading System ID at address 0x10002020: ID value does not match: read 0x50CA161A; expected 0x3D312F3A Timestamp value does not match: image on board is older than expected Read timestamp 15:08:53 2010/08/04; expected 19:10:40 2010/09/25 The software you are downloading may not run on the system which is currently configured into the device. Please download the correct SOF or recompile. Leaving target processor paused There are no Nios II CPUs with debug modules available which match the values specified. Please check that your PLD is correctly configured, downloading a new SOF file if necessary. If you know any solution to this, I will greatly appreciate it. Thanks in advanceLink Copied
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what a beast...
me too- Mark as New
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LoL... I tried switching back to Nios II/e.. The ID mismatch problem is rectified, but timestamp is still mismatched...
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After you modify the Nios CPU type, you must run SOPC builder to regenerate the system, and then Quartus to recompile the design. Then you must reconfigure your FPGA with the new SOF file (and be careful, if you don't have the license, the design will be compiled in a different .sof file, with "_time_limited" added to the name).
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I see.. I think the problem was not having a licence. I might contact my univ for help, but thanks for your expertise
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You can still do some tests without a license. You'll just have an opencore evaluation window that opens when you configure the FPGA, and you'll have to keep the USB cable connected during your test.
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