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Altera_Forum
Honored Contributor I
1,766 Views

DE0: Nios 2 with custom logic and PIO.

Hi, 

I'm just getting started with the DE0-board. (Cyclone III). My goal is to have a Nios 2 soft core processor together with UART. I also want the Nios processor to act master on the avalon bus communicating with custom logic (through PIO?). I've tried to go through the Nios II Hardware Development Tutorial (step by step), but I get error message when I'm trying to run as hardware. The error message tells me there's a mismatch of timestamp. Anyhow, does anyone know a great tutorial for my goal of having a soft processor communicating with custom logic through the bus? 

 

Kinds regards, 

mr_embedded
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7 Replies
Altera_Forum
Honored Contributor I
43 Views

The timestamp mismatch means that the SOPC project that is configured inside the FPGA isn't the same than the one your software was compiled for. Be sure to accomplish the following tasks, in that order: 

  • Generate the system from SOPC builder, save and quit SOPC builder 

  • Compile the design in Quartus 

  • Program the FPGA with the compiled project 

  • Compile your system library (old IDE) or regenerate your BSP (new IDE) 

  • Compile your software 

  • Download your software 

 

With the old IDE the system library is automatically rebuilt when there is a change in the SOPC project each time you 'make' your application, but it seems that with the new one you need to regenerate the BSP manually.
Altera_Forum
Honored Contributor I
43 Views

Daixiwen thanks a lot for your answer! 

 

One thing remain, does anyone have a great step by step tutorial of how I set up my own .vhdl file to the interface to Avalon bus? Basically I have 8 bits in my .vhdl file that I want to receive from my Nios II processor. It's a PWM signal that the .vhdl file generates and the 8 bits is the upper limit of the counter. So all signals like read/write etc. a tutorial for that would be great. 

 

Regards, 

mr_embedded
Altera_Forum
Honored Contributor I
43 Views

Have a look at chapter 10 of that document (http://www.altera.com/literature/ug/ug_sopc_builder.pdf). 

For a simple compenent like yours, you should just need a 'write' signal (std_logic) and a 'writedata' signal (std_logic_vector) on your avalon slave interface. They are both inputs, and when write is '1', read the contents from 'writedata'. 

You should also have a clock input interface (clock and reset signals) and a conduit interface for the PWM signal that you generate.
Altera_Forum
Honored Contributor I
43 Views

Thanks again Daixiwen. I want to go through the walkthrough at chapter 10 as you told me to but early on, are they referring to: Design files for the example design—A hyperlink to the design files appears next  

to this user guide, on the SOPC Builder literature page. 

 

I can't find those example files :( 

Any idea where I can find them? 

 

regards, 

mr_embedded
Altera_Forum
Honored Contributor I
43 Views

I'm not sure... they should be on this page (http://www.altera.com/literature/lit-sop.jsp) but I can't see them. Even in the "Related documentation" section. It seems that they forgot to move them when putting everything in the SOPC builder manual...

Altera_Forum
Honored Contributor I
43 Views

I'm quite proud of my self solving my previous issue. Thanks for your time Daixiwen. Maybe you could give me some input to my latest obstacle to tackle? Its located here on the forum: 

http://www.alteraforum.com/forum/showthread.php?t=27227 

 

Thanks a lot! 

// mr_embedded
Altera_Forum
Honored Contributor I
43 Views

I have no idea, sorry dude!

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