Intel® FPGA University Program
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DE2 Ethernet problem

Altera_Forum
Honored Contributor II
1,310 Views

hi everyone,I am trying to use DE2 board to realize the net communication.First I use the example project in the CD,the project runns well.then I build a new project and add the DM9000A,but now I can't tranmit nor recieve from the net,I have tried to use every method I know ,but still I can't solve the problem,is there anything that I have't pay attention to?Thank you.

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Altera_Forum
Honored Contributor II
572 Views

Hi. 

You should provide more info about your problem. To let us help you.
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Altera_Forum
Honored Contributor II
572 Views

Hi: 

thank you for your patent reply here and in the nios forum. 

The project's size is 20MB,even when I compress it into zip format ,it's size is 11MB,so I don't think I can upload it here. 

I still want to send the project to you,because I think if you have the complete project,you could give a minute description. 

My email address is lijianfei2006@gmail.com, if possible,could you send me a E-mail,then I could know your email address and send my project to you? 

I am looking forwad to you reply,thank you!
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Altera_Forum
Honored Contributor II
572 Views

It's so heavy for email, maybe you could upload it at rapidshare.com 

Also there are ways to send full project in very small sizes. 

Regards. 

Alberto.
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Altera_Forum
Honored Contributor II
572 Views

Hi swordflyer. 

First error, you used clk_50 for DM9000, in the DE2_NET uses 100Mhz, in this way you´ll get the 25Mhz clock for the DM9000 PHY chip. 

Try correct this, and then told me.
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Altera_Forum
Honored Contributor II
572 Views

Hi: 

I have solved the problem with your method,Thank you very much.
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Altera_Forum
Honored Contributor II
572 Views

I am having a similar problem; however, reception is giving me trouble. I am using the DE2 to send acknowledges to a host PC when packets are received. The project requires the DE2 to receive modified ASCII characters, addresses to the character ROM, and store them in memory for display on a Terasic LCD. Everything is coming together with the exception of receiving packets.  

 

The full problem is the DE2 will receive one packet, then the system crashes. The strange part is the ISR exits, which I've tested with the JTAG UART, but transmission and reception (the whole system really) stops functioning; but the system will print one last time before dieing, very strange, but not hit the end of code. Help with getting me on track would be greatly appreciated.
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