Hi, I'm new at forum and with the fpga. I am trying to make the migration from sopc to qsys of the project demonstration de2_70_net. I wanted to know where I can find information about it or a tutorial. I am currently using version 13.0.1 of quartus II.Thank you for your time. A greeting.
Hi,Refer https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an632.pdf https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an748.pdf Let me know if this has helped resolve the issue you are facing or if you need any further assistance. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)
hi again,the information was very helpful, I managed to perform the conversion and compilation without errors but I have a new problem when it comes to wanting to run the demonstration: - I charge the program in fpga in quartus II <13.0.1>. - I open nios II Software Build Tools for eclipse. - I create a new project in Blank and name the folder <web and web_bsp> - In Windows(OS) I copy the files from : "software">>"DE2_70_net" to the "software">>"web" - I refresh the "web" folder in eclipse - I right click on web_bsp and: niosII >> generate bsp - right click on web: build project - right click on web: run as >> 3 Nios II Hardware At this point with the original project (SOPC) I can see the packages, but now with the new project nothing is displayed even though no errors appear. LINK project: http://ge.tt/4slhxmp2 i can't upload a project with forum's attachments tool. Thanks for your time, Regards.
Hi,Apologies for late reply. we can see this problem when we try to open eclipse project which is created in a different version eclipse. So try to create new rather than importing project. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)
Hello,I recently got a migration that works despite having a small error in the order in which the 7 segments are displayed. The biggest problem I found was finding out that Qsys alters certain lines of code, but reviewing a bit in this forum and with the help of altera wiki I made the following changes: these names were modified in the qsys generated file: pll_c0_system -> pll_c0_out pll_c1_memory -> pll_c1_out pll_c2_audio -> pll_c2_out Once renamed to its original form make the changes mentioned in: http://www.alterawiki.com/wiki/new_qsys_issues#wrong_vhdl_example_in_qsys_for_different_blocks With these changes the rest was only to review and add to the project of quartus the file alt_pll.qip of the original project. At this time the project performs the functions of sending and receiving packages but I am not happy with that error of the 7 segments. I leave the project link. I will keep you informed as I progress. http://ge.tt/24w3vfp2 Best Regrads.