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Hi, I am working on implementing the FFT megacore in my project and I am seeing a problem with the source_error. Here is the info on my FFT:

Burst Architecture Single Output Engine Transform Length of 8192 Data Precision of 16 bits Twiddle Precision of 16 bits Targeting the Cyclone IV Here are my problem: I assert sink_sop, sink_valid, I start transferring data to the FFT and then 8192 clock cycles later (8192 because that is my transform length) I assert the sink_eop. One clock later, the source_eop got assert and I am getting source_error message 10(Missing EOP) and one clock later source_error message 01 (Missing SOP). So my question is, what am I doing wrong?Link Copied

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--- Quote Start --- Hi, I am working on implementing the FFT megacore in my project and I am seeing a problem with the source_error. Here is the info on my FFT: Here are my problem: I assert sink_sop, sink_valid, I start transferring data to the FFT and then 8192 clock cycles later (8192 because that is my transform length) I assert the sink_eop. One clock later, the source_eop got assert and I am getting source_error message 10(Missing EOP) and one clock later source_error message 01 (Missing SOP). So my question is, what am I doing wrong? --- Quote End --- You are probably 1 cycle too late on your EOP signal. Try moving it ahead by one clock and see if it works. Pete

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When assert the SOP and valid signals together, it determine the first sample data is appeared in data signals, when assert the EOP and valid signals together, it determine the last sample appear at data signals. Please ensure there are 8192 data sample available, where the first one and last one are align with SOP and EOP.

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Well, thanks for your answers.

You have been right Pete, the problem came from 1 cycle too late on the EOP signal. But now, I have another problem. Indeed, I don't have any more source_error, actually, there isn't any activity on any source_signal. Even 2.5 ms after the last data being transferred. So do you know what is wrong now? Hope to read you soon.- Mark as New
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Do you have your source ready = 1'b1?

That would cause what you are seeing. Pete- Mark as New
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Yes, this signal always is at '1'.

I'm wondering if the problem can come from the fact I have no output buffer (only input buffer to load the data but no output buffer to load the results). This's because I want to know if everything is alright with my input design before coding the rest of my design.- Mark as New
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If you are running RTL Simulation this shouldn't matter. But if you are running a gate level simulation, if you do not have the outputs connected to something in the design, they will get optimized out.

If you are just running RTL Simulation, try running more than one set of data into the FFT core. Pete- Subscribe to RSS Feed
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