Hi Friends,I have the Terasic DeE-0 Nano Development board with Cyclone V and ARM Cortex HPS. As a part of my project, I have send some huge amount of data ( in megabytes ) from FPGA to HPS and store it in the SDcard in the HPS system whichis running Linux on it. I have used the HPS Component and "External Bus to Avalon Bridge" to connect from FPGA Fabric to SDRAM, so that I can send the data through the exported external interface. Now, the problem is I am getting an error with memory range. The screenshot is attached. These are the Qsys messages and the first line is the error message.
Error: FPGA2SDRAMAVEXBRIDGE.HPS_SDRAM.avalon_master: HPS_Host.f2h_sdram0_data (0x0..0xffffffff) is outside the master's address range (0x0..0x3fffffff) Warning: FPGA2SDRAMAVEXBRIDGE.HPS_Host: "Configuration/HPS-to-FPGA user 0 clock frequency" (desired_cfg_clk_mhz) requested 100.0 MHz, but only achieved 97.368421 MHz Warning: FPGA2SDRAMAVEXBRIDGE.HPS_Host: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies. Warning: FPGA2SDRAMAVEXBRIDGE.HPS_Host: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity Warning: FPGA2SDRAMAVEXBRIDGE.HPS_Host: set_interface_assignment: Interface "hps_io" does not exist Info: FPGA2SDRAMAVEXBRIDGE.HPS_Host: HPS Main PLL counter settings: n = 0 m = 73 Info: FPGA2SDRAMAVEXBRIDGE.HPS_Host: HPS peripherial PLL counter settings: n = 0 m = 39This is the problem. Does somebody have an idea how to resolve it ?. Or if can suggest me some other way it would be greatly appreciated. I am parallelelly trying a DMA , but the above solution would be more convenient for me.
Hello,Let read error message again and try to understand it. Your HPS_SDRAM's Avalon master's address width is 30 bits ( to address 0x0 to 0x3FFF_FFFF, 30 bits are required. ) while avalon slave to which you are trying to connect your master requires 32 bits ( to address 0x0 to 0xFFFF_FFFF, 32 bits are required.) Hence this error message is reported. One possible way to solve this is to increase address width for your avalon master. Double click on your HPS_SDRAM component and see whether it is possible to increase its address width. Thank you, Bhaumik
Hello Bhaumik,I tried that option in the Qsys. Unfortunately the maximum achievable address using the Avalon master is 2^30. I wonder how th Qsys allows the connection between these component. Do you suggest anything else? Best Regards.
Hello,Then could you check whether you have configured your slave component correctly or not? Does it really need 32 bit address width? Warm Regards, Bhaumik
Hello,Yes, the the f2h_sdram_data is the Avalon slave. I connected the Avalon_master of the bridge to this slave port. I am able to connect, but only problem is the memory mismatch. Could you please tell what do you mean by "Does it really need 32 bit address width" ? Do you mean the slave requires the 32 bit address width ? if so, no the maximum can be configured is 29 bits. But even though, how will I connect these two ports. Is there any documents tutorials for this ? I could not find anything which shows Qsys configuration,unfortunately. Best Regards.
Hi,From following ( http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=165&no=941&partno=2 ), I came to know that board which you are using has 1 GB DDR3 SDRAM memory. Now, to represent this memory, we do not need 32 bit address width. ( It's data bus is of 32 bits.) I just want you to see how you have selected Address width for your f2g_sdram_data. Is it really configured for 1GB memory or something else? Kind Regards, Bhaumik