Flash Memory and SRAM data pin assignment

[Altera_Forum]

Hi, 

 I'm having problem in assigning pins in using flash memory and SRAM. In my sopc, I'm using one avalon mm tristate bridge to link to the SRAM and Flash. Im not sure where should I assign the data pins for flash memory. The details of SRAM and flash are  SRAM: 256K x 16bit Flash: 4M x 8 bit  Once I generated the processor and updated it in bdf in quartus, the output from the processor are:  address_to_the_cfi_flash[21..0] chip_select_to_the_static_ram_0[21..0] read_n_to_the_cfi_flash read_n_to_the_static_ram_0 select_n_to_the_cfi_flash tristate_bridge_address[17..0] tristate_bridge_byteenablen[1..0] tristate_bridge_data[15..0] write_n_to_the_cfi_flash write_n_to_the_static_ram_0  where should I assign the data pins for flash memory and SRAM?  Thanks

[Altera_Forum]

Lower 8 bits of tristate_bridge_data to both devices, upper 8 only to the SRAM. Be sure to connect the byteenable signal to the SRAM, as well. 

 Cheers,  - Ura

[Altera_Forum]

I have tried to assign the lower 8 bit for both flash and sram, and upper 8 bit assign only to sram. However, I have problem compiling the bdf file. Can you please guide me in resolving this error? Thank you. 

http://img229.imageshack.us/img229/7027/bdfkm0.th.png (http://img229.imageshack.us/my.php?image=bdfkm0.png)

[Altera_Forum]

I'm having the same problem with Cyclone III Development Kit. Using 2 tri-state bridges connected to a SSRAM and FLASH. 

 I would certainly need a step-by-step guide to do this. I've been fiddling with this for some time now :mad:  Do I specify the shared pins in the Pin Planner?  Thanks in advance!