Four Bit Ripple-Carry Adder Circuit DE1

[Altera_Forum]

I've got some of the code from the website and some from my own from a Full Adder Circuit.It seems like my code is mixed up as when i insert output A or B,instead of having a sum,i have an output.This is wrong according to the truth table.Can anyone have a look at my code? 

 LIBRARY altera; USE altera.maxplus2.carry;  LIBRARY ieee; USE ieee.std_logic_1164.ALL;  LIBRARY WORK; USE WORK.usr_def.ALL;  ENTITY chiong3_1 IS   PORT(  x_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);  y_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);  c_in : IN STD_LOGIC;  sum : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);  c_out : OUT STD_LOGIC;  red : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)); END chiong3_1;  ARCHITECTURE struct OF chiong3_1 IS SIGNAL im : STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL imi : STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN   red <= c_in & y_in & x_in;   c0 : full_add --1st starting fa  port map (x_in(0),y_in(0),c_in,sum(0),im(0)); --im(0) is c1  c01 : carry   port map (im(0),imi(0));  c : for i in 1 to 2 generate  c1to2: full_add   port map (x_in(i),y_in(i),  imi(i-1),sum(i),im(i));  c2to3: carry   port map (im(i),imi(i));  end generate;  c3 : full_add   port map (x_in(3),y_in(3), --last starting fa  imi(2),sum(3),c_out); --im(2) is c3 end struct;  ------------------------------------------------------- Library ieee; USE ieee.std_logic_1164.ALL;  PACKAGE usr_def IS  COMPONENT full_add   PORT(  A,B,carryin : IN STD_LOGIC;  carryout,sum : OUT STD_LOGIC);  END COMPONENT; END usr_def; -------------------------------------------------------- Library ieee; use ieee.std_logic_1164.all;  entity full_add is  port(A,B,carryin :in std_logic;  carryout,sum:out std_logic); end full_add;  -------------------------------------------------------- architecture behavior of full_add is begin    sum <= A xor B xor carryin ; carryout <= (A and B) or ( B and carryin) or (carryin and A);    end behavior;