Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
1,009 Views

Help! Simulation Vector Output Issue

Gurus for this forum,  

 

I'm a student doing an ASICS and FPGA module at college in the UK and one of my tasks is to build a device using the drag and drop method, no vhdl allowed :( and if im honest, im not that confident using the quartus tools yet, so no doubt this is a newbie question. 

 

The device is a simple alarm clock and to be designed with typical ASM methods, the project was going well until now when im trying to test the control logic. 

 

Im finding that a few of my vector outputs are showing the hashed pattern symbolising 'forced unknown'. The first instance occurs with a simple SR register in that on setting (1 clock pulse on s) the q will go high one clock later but then one clock after that (1 clock after s goes low again) Q shows the forced unknown pattern, which makes other dependant logic signals forced unknown when their conditions are met for the remainder of the simulation waveform file. 

 

I have tested the SR register independently and a single independent SR Flip-Flop , and it is behaving the same when signalled with the same pulse width via a vectored input pin. ie. appears high for the pulse width (1 clock skew) and then forced unknown there after. 

 

Could this be a design error? or caused by Quartus a setting? can anyone advise? 

 

thanks for your time. 

 

# Luke
0 Kudos
4 Replies
Altera_Forum
Honored Contributor I
9 Views

 

--- Quote Start ---  

Could this be a design error? 

--- Quote End ---  

It sounds like.
Altera_Forum
Honored Contributor I
9 Views

Then why does the problem manifest with a simple quarts library part too?

Altera_Forum
Honored Contributor I
9 Views

Made a new project and copied the file, renamed it and its now working fine. 

 

 

WTF 

 

 

Thanks anyway guys
Altera_Forum
Honored Contributor I
9 Views

the top way is the best way to try it ! 

good luck!