Hi, there, I'm working on Altera's VHDL Lab Exercises, Lab7 Part1. I can not find any module named altsyncram in LMP. Can anyone suggest to me what to do?
If it's the Lab 7 called"Implementation of UART and Timer Circuits" then you don't use the altsyncram device for RAM. The only RAM needed is onchip memory allocated in the SOPC builder.