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Hi, there, I'm working on Altera's VHDL Lab Exercises, Lab7 Part1. I can not find any module named altsyncram in LMP. Can anyone suggest to me what to do?
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If it's the Lab 7 called
"Implementation of UART and Timer Circuits" then you don't use the altsyncram device for RAM. The only RAM needed is onchip memory allocated in the SOPC builder.- Mark as New
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altsyncram = ram 2 ports
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That's not true. altsyncram can be a dual-port RAM if you want it to be, but it can also be a single-port RAM. And it's not the question that was asked.

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