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SCort7
Beginner
379 Views

How can I fix it? (integer input/output)

Hi, i have a problem when I want to simulate a programme that is only a division between two integer values. The compilation of the code is correct, but in the simulation appears this error:

 

# ** Fatal: (vsim-3807) Types do not match between component and entity for port "Dato1".

 

 

I don´t know what to do. Help please. Bellow is attached the programme.

 

library IEEE;

use ieee.std_logic_1164.all;

 

entity UnsignedProject is

port

(

D1: in integer range 0 to 15;

D2: in integer range 0 to 15;

Res: out integer range 0 to 15

);

end UnsignedProject;

 

 

architecture Behavior of UnsignedProject is

 

begin

 

Res <= D1 / D2;

 

end Behavior;

 

 

 

 

0 Kudos
1 Reply
AnandRaj_S_Intel
Employee
38 Views

Hi,

 

  1. Delete db, incremental_db and simulation folder from the project directory.
  2. Run a full compilation of the Quartus project.
  3. Include the numeric library.

 

Regards

Anandsimlation.JPG

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