Hello there ,
Apologize for delay in response ,
I agree with your concern and I tried to look at I didnt find the twc value mentioned in the datsheet or userguide.
but can we do the design and using the time quest do the timing analysis to make latch flop at the memory match clock is given.
Also would it possible to do the gate level simulation to see the timing and any data contention ?
Thank you ,
Hello Sudodh ,
Sure ..I will let the internal team know about this and make sure we are not missing anything.
Thank you again for understanding the situation :)