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Beginner
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How to setup DE10 Lite for ADC with Potentiometer?

I recently purchased a DE10 Lite board and currently trying to set it up to read voltage from a potentiometer. I am not sure if I need to do anything special to accomplish this. However, I saw some documentation regarding the platform designer which seem to suggest that I need to configure the board. When I tried using the instructions, I was not able to move beyond point just before generating the HDL. Does anyone have a detailed step by step instruction specifically for a DE10 Lite?

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Employee
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Hi ,

I understand your concern, is it possible to be more specific , which document you are referring and where you been stuck . So that I can guide from there

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Beginner
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First of all, do I need to do any special configuration with the De10 Lite FPGA in order to read the analog voltage from a 10k ohm potentiometer voltage divider setup. If the answer is yes, then can you provide me with specific detailed instructions on how to proceed? If the answer is no, then can you point me to the document that can help me with the setup.

 

Thanks.

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Beginner
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The document is the platform designer.

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Employee
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Hi ,

Kindly find my analysis from my understanding of your question.

  

1. do I need to do any special configuration with the De10 Lite FPGA in order to read the analog voltage from a 10k ohm potentiometer voltage divider setup

>> From the above I think you need to connect a potentiometer to a Pin in ADC, This will convert the analog signal to digital signal.

2. then can you provide me with specific detailed instructions on how to proceed? If the answer is no, then can you point me to the document that can help me with the setup

>> This one you have to call/instantiate ADC IP in your design.

 

If you are using a platform designer, I am requesting to check the user guide for the platform designer.

I am sharing the documents which is useful for quick start to work in platform designer.

 

https://www.intel.com/content/www/us/en/programmable/products/design-software/fpga-design/quartus-pr... 

 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an812.pdf

 

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