Is there a best practise to build a Clock Synchronizer for a Cyclone IV or V?

[Altera_Forum]

I'm teaching techniques to cross clock domains (CDC), and I need to develop some demonstrators. 

 For some techniques, you would cascade D-Type FlipFlops without any combinational logic between them. These D-Types also need to be as close as possible, and have the fastest setup time possible of course.  We are using a Cyclone IV on a DE0-Nano board, but I assume the issue is the same for the DE1 boards (which we will move to next year)  It's straightforward to write VHDL to build a clock synchroniser. The issues I am uncertain about is how to constrain the synthesis to minimise mtbf.  Maybe there is a standard component that allows me to build a clock synchroniser? (I could not find one).  Many thanks in advance.

[Altera_Forum]

--- Quote Start ---  I'm teaching techniques to cross clock domains (CDC), and I need to develop some demonstrators.  For some techniques, you would cascade D-Type FlipFlops without any combinational logic between them. These D-Types also need to be as close as possible, and have the fastest setup time possible of course.  We are using a Cyclone IV on a DE0-Nano board, but I assume the issue is the same for the DE1 boards (which we will move to next year)  It's straightforward to write VHDL to build a clock synchroniser. The issues I am uncertain about is how to constrain the synthesis to minimise mtbf.  Maybe there is a standard component that allows me to build a clock synchroniser? (I could not find one).  Many thanks in advance.  --- Quote End ---    I wire two registers directly...and leave it to tool. The ideal is balanced setup/hold rather than best setup. You may therefore add max/min delay on that path to target balanced timing but I never done that. you also need false path at cross over. dual clock fifos sdc may give better details.

[Altera_Forum]

Check out the Managing Metastability chapter in the Quartus Prime handbook: 

 https://www.altera.com/products/design-software/fpga-design/quartus-prime/support.html

[Altera_Forum]

--- Quote Start ---  I wire two registers directly...and leave it to tool. The ideal is balanced setup/hold rather than best setup. You may therefore add max/min delay on that path to target balanced timing but I never done that. you also need false path at cross over. dual clock fifos sdc may give better details.  --- Quote End ---    Altera Dual clock fifos had false paths across the clock domains embedded in the core until recently. I think there is now an idea that some people would rather put a max delay constrain across the path rather than a false path, as this would prevent the tool placing the false paths registers at opposite ends of the chip (though this is unlikely, its not beyond the realms of probability). The problem with the embedded constraint is that it cannot be overridden, as false path always takes priority.  From the DC fifo user guide, https://www.altera.com/en_us/pdfs/literature/ug/ug_fifo.pdf, P21, you can see this new option is from Q15.1+ and only applies to arria 10. If you have an older device, you're stuck with a false path.