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EFroh
Beginner
303 Views

Issue with regenerating synthesis for IP cores in the project

Hi,

I have Top Qsys with some generic components.

When I'm trying to change the "IP Regeneration Policy" on the IP settings to "Always regenerate design files for IP cores" the generic components are not regenerate.

 

Do you have a solution for this, except for the opening the QSYS and generate ?

 

Thanks.

0 Kudos
9 Replies
80 Views

Hi,

 

Are you adding the .qsys file or .qip in the project directory?

 

Thanks.

EFroh
Beginner
80 Views

Hi,

 

I'm adding the .qsys file.

Thanks.

80 Views

Hi,

 

The software will automatically regenerate the Qsys system during the compilation if you add .qsys file to the project directory. When the Intel Quartus Prime software starts the Analysis & Synthesis phase, it processes the .qsys files and generates the necessary HDL and system description files needed to compile your design.

 

Thanks.

EFroh
Beginner
80 Views

Hi,

It doesn't work with .qsys file.

 

Thanks.

80 Views

Hi,

 

Could you share the steps to check whether it is regenerate or not?

 

Thanks.

80 Views

Hi,

 

Do you have any updates?

 

Thanks.

EFroh
Beginner
80 Views

Hi,

I created Qsys Top level file with generic components.

I'm trying to update the RTL files in the path the generic component's TCL file point to.

I changed IP generation settings to "Always Regenerate design files for IP cores"

I started compilation.

Generic component file was not updated. And all the synth directory was not updated.

 

In short, When I have <ip_name>.ip and don't have <ip_name> synth directory of generic component IP. When running, as described above. It failed with error "<ip_name> not found"

 

Thanks.

 

 

80 Views

Hi,

 

Do you mean that you are trying to modify the HDL file of the IP? If yes, you have to include the .qip file instead of .qsys file

 

Thanks.

80 Views

Hi,

 

May I know if you have any updates?

Thanks.