I've been trying to figure out what's wrong with my design for lab8 part 2. I've implemented the RAM LPM and a hex 7segment driver but I can't seem to get it to work in my process.
Can anyone help explain?
My top-level design, where the problem exists:
entity part2 is
KEY : in unsigned(0 downto 0);
SW : in unsigned(17 downto 0);
LEDG : out unsigned(0 downto 0);
HEX1, HEX0 : out unsigned(6 downto 0)
architecture behavioral of part2 is
signal Qout : unsigned(7 downto 0);
signal addr : unsigned(7 downto 0);
signal wSig : unsigned(0 downto 0);
--signal clk : unsigned(0 downto 0);
signal data : unsigned(7 downto 0);
signal crap : unsigned(3 downto 0);
--disregard these switches
crap(3) <= SW(16);
crap(2 downto 0) <= SW(10 downto 8);
process(KEY, SW, wSig) begin
if(KEY = "0") then
wSig <= SW(17 downto 17);
--clock input and signification
LEDG <= "1";
if(wSig = "1") then
addr(4 downto 0) <= SW(15 downto 11);
addr(7 downto 5) <= "000";
data <= SW(7 downto 0);
mem : entity work.ramlpm port map(address => std_logic_vector(addr(4 downto 0)),
clock => KEY(0), data => std_logic_vector(data),
wren => wSig(0), unsigned(q) => Qout);
seg0 : entity work.HEX port map(Qout(3 downto 0), HEX0);
seg1 : entity work.HEX port map(Qout(7 downto 4), HEX1);
seg4 : entity work.HEX port map(data(3 downto 0), HEX4);
seg5 : entity work.HEX port map(data(7 downto 4), HEX5);
seg6 : entity work.HEX port map(addr(3 downto 0), HEX6);
seg7 : entity work.HEX port map(addr(7 downto 4), HEX7);
The generated memory block LPM(I've taken the copyright info out of this file in order to fit it into one forum post. I apologize if this might cause any issues.)
See attached for the generated memory block of LPM
See attached for the 7 seg code
thanks for the reply, according to the lab, i have to use KEY0 as a clock input. and yes, the LED is stuck at 1 :). I can't figure out what i'm doing wrong here.
Currently, you are not using KEY0 as a clock, you are just using it as an enable (active low). At the moment if anything changes while KEY0 is '0' then the output will change too. To be a clock, you need to change outputs on the rising/falling edge of that signal. You can do that by:if rising_edge(KEY0) then... --or falling_edge(), but not both If KEY0 is not a real clock, but a signal generated elsewhere, you could run into problems with setup and hold times. You need a globally distributed signal to act as a proper clock (which is usually an actually clock). With LEGD, you set it to '1', but you never set it back to '0'. So the first time KEY0 is '0', LEGD gets latched to '1' and never changes.
Hello,Work and life have kept me from my hobby, even though it's been scratching at the back of my mind all this time. So now i finally have a chance to look at this stuff again and I'm having trouble with type conversion. Taking your advice, Tricky, I've changed my if to: --- Quote Start --- if(rising_edge(KEY)) then --- Quote End --- But this gives me the error: --- Quote Start --- Error (10476): VHDL error at part2.vhd(35): type of identifier "KEY" does not agree with its usage as "std_ulogic" type --- Quote End --- So then i try to change this to: --- Quote Start --- if(rising_edge(std_logic(KEY))) then --- Quote End --- But I get an error saying: --- Quote Start --- Error (10305): VHDL Type Conversion error at part2.vhd(35): cannot convert type "UNSIGNED" to type "std_logic" --- Quote End --- I've googled VHDL type conversion for over an hour now and can't seem to find an answer. For all its type safety, VHDL design practice documentation seems to lack very much. Could someone please help?
you've declared key as an unsigned which is an array. std_logic is not, so you can't type convert. because unsigned is just an array of std_logic, you just need to index a single element.if rising_edge(key(0)) then ...
Ahh, Yep, can't believe I missed that. Sorry :)Now i just guess it's back to figuring out how to get this "clock" to actually work. I guess I'll use this thread to document my progress.