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Shiva
Beginner
1,061 Views

MAX 10 FPGA Remote System Upgrade (RSU)

Hi,

I am trying remote system upgrade for MAX10 FPGA device, Here i am able to write and read the rpd data of CFM1 but when i trigger the reconfiguration it is not getting reconfigured. I am doing this remote system upgrade without using the NIOS ii processor.

Can you provide the information regarding, is there any particular way to write the rpd data to configuration flash memory of MAX10 FPGA device and what might be the reason for not getting reconfigured?

Thanks,

Shiva

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47 Replies
JohnT_Intel
Employee
207 Views

Hi.

 

May I know how do you trigger the reconfiguration? Do you change the "config_sel_overwrite" bit and "config_sel" bit on Dual Configuration IP before triggering reconfiguration?

 

You may refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_config.pdf table 34.

 

Shiva
Beginner
207 Views

Hi John,

 

Thanks for the reply.

 

yeah i changed the "config_sel_overwrite" and "config_sel" bits to high and then triggered the reconfiguration but it is not getting reconfigured.

 

Here if i flash the .pof file which contains both factory image and application image it is reconfiguring but if the send the RPD data of CFM1 to on chip flash memory through avalon memmory mapped interface and if i trigger the reconfiguration it is still at CFM0(not reconfiguring). The .pof and .rpd files are generated by using the Quartus prime 16.0 lite edition. Does it makes any difference with .pof and .rpd files.

 

Regards,

shiva

 

 

JohnT_Intel
Employee
207 Views

Hi,

Could you provide the step that you performed to reconfigure the device? Have you try to read the offset 3 and offset 7 of the Dual Configuration IP?

Shiva
Beginner
207 Views

Hi,

 

Here is the reconfiguration code.

 

 

//Reconfiguration block

module reconfig_block

(input clk_20mhz,rst,

 input reconfig_en

 );

 

 

 //dual boot signals

 reg[2:0]dual_address;

 reg dual_read;

 reg[31:0]dual_writedata;

 reg dual_write;

 wire[31:0]dual_readdata;

 

 reg led;

 

 

 

 reg [3:0]state;

 parameter configoverwrite_config_sel = 4'b0000,

  status_read  = 4'b0001,

  status_read0  = 4'b0010,

  status_read1  = 4'b0011,

  status_read2         = 4'b0100,

  status_read3         = 4'b0101,

  status_read4         = 4'b0110,

  status_read5  = 4'b0111,

  trigger_reconfiguration  = 4'b1000;

  

 

dual_configuration_ip_core u0 (

.avmm_rcv_address   (dual_address),  // avalon.address

.avmm_rcv_read    (dual_read),   //    .read

.avmm_rcv_writedata (dual_writedata), //    .writedata

.avmm_rcv_write    (dual_write),   //    .write

.avmm_rcv_readdata  (dual_readdata), //    .readdata

.clk         (clk_20mhz),        //  clk.clk

.nreset        (!rst)       // nreset.reset_n

);

 

 

 

always@(posedge clk_20mhz, posedge rst)

 begin

if(rst)

begin

state <= configoverwrite_config_sel;

dual_write <= 1'b0;

dual_writedata <= 32'h00000000;

dual_read <= 1'b0;

dual_address <= 3'b001;

end

else

begin

case(state)

configoverwrite_config_sel : if(reconfig_en)

begin

dual_address <= 3'b001;

dual_write <= 1'b1;

dual_writedata <= 32'h00000003;

state <= status_read;

end

status_read : begin

dual_write <= 1'b0;

dual_address <= 3'b011;

dual_read <= 1'b1;

state <= status_read0;

end

status_read0 : if(dual_readdata[0] != 1'b1)

begin

state <= status_read;

end

else

begin

state <= status_read1;

end

status_read1 : if(dual_readdata[0] == 1'b0)

begin

dual_address <= 3'b010;

dual_write <= 1'b1;

dual_writedata[3] <= 1'b1;

state <= status_read2;

dual_read <= 1'b0;

end

status_read2 : begin

dual_write <= 1'b0;

dual_address <= 3'b011;

dual_read <= 1'b1;

state <= status_read3;

end

status_read3 : if(dual_readdata[0] != 1'b1)

begin

state <= status_read2;

end

else 

begin

state <= status_read4;

end

 

status_read4 : if(dual_readdata[0] == 1'b0)

begin

dual_address <= 3'b111;

dual_read <= 1'b1;

state <= status_read5;

end

status_read5 : if(dual_readdata[1:0] == 2'b11)

begin

state <= trigger_reconfiguration;

dual_read <= 1'b0;

end

else

begin

state <= status_read5;

end

trigger_reconfiguration : begin

dual_address <= 3'b000;

dual_write <= 1'b1;

dual_writedata <= 32'h00000001;

led <= 1'b1;

end

endcase

end

end

endmodule

 

 

i am able to reconfigure with the .pof file flashed through JTAG but not with .rpd data sent through avalon memory mapped interface.

 

 

 

 

JohnT_Intel
Employee
207 Views

Hi,

May I know how do you send the rpd file through Avalon-MM interface? Are you using little-endian or big-endian file?

Shiva
Beginner
207 Views

Hi,​

I​ am receiving rpd data from external STM32 micro controller to FPGA through SPI interface and from here to onchip flash memory through Avalon memory mapped interface. Here I am collecting 4bytes of data from micro controller and then sending it to onchip flash memory(CFM1 & CFM2). The total size of rpd file is 140KB.I am using little-endian file.

Regards,

Shiva​.

JohnT_Intel
Employee
207 Views

Hi,

 

Have you try to read back the content of the flash? Could you try to use big-endian file?

Shiva
Beginner
207 Views

Hi,

 

Yes, i able to read the content of flash memory and the data what i am reading is exactly matching with the rpd data. I tried with the big-endian file but still it is not getting reconfigured. The big-endian option was selected by going through Convert programming files -> options/Boot info -> rpd file endianness -> Big endian.

 

Regards,

Shiva.

JohnT_Intel
Employee
207 Views

Hi,

 

May I know if you update CFM1 and CFM2? Could you provide me the step that you use to update it?

Shiva
Beginner
207 Views

Hi,

 

I am updating CFM1 and then CFM2.

 

ERASE OPERATION:

Before writing data to CFM1 and CFM2, i am erasing the on chip flash memory(CFM1 & CFM2) by disabling the write protection and giving the sector to be erased and then enabling the write protection.

 

WRITE OPERATION:

After erase operation i am disabling the write protection of CFM1 sector and giving the starting address, write enable and write data, burst count to '1'(parallel) and continuing this process till it reaches the end address of the CFM1 sector and then enabling the write protection of CFM1 and disabling the write protection of CFM2 and continuing the above process till it reaches the end address of CFM2 and enabling back the write protection.

 

READ OPERATION:

After write operation i am disabling the respective sectors write protection ,giving the address,burst count to '1'(parallel),read enable and waiting for the readdatavalid and then collecting the data. I am continuing this process by incrementing the address till i receive the entire data.

 

RECONFIGURATION:

After all these i am triggering the reconfiguration.

 

In each and every operation i am checking the erase success,write success and read success.

 

NOTE: Here the read operation is performing only to verify the data.

 

Regards,

Shiva.

JohnT_Intel
Employee
207 Views

Hi,

 

From your information provided, the step looks correct and I assume that the data is written correctly to CFM1 and CFM2. Could you read the msm_cs value of the dual boot IP?

Shiva
Beginner
207 Views

Hi,

 

I tried to read the msm_cs value from dual boot ip by giving the offset 4, the dualboot ip is giving all 1's from [16:0] and all 0's from [31:17](checked in the simulation). Which means the msm_cs value is 1111 (16:13). This indicates it is not matching with any msm_cs values.How can i get the correct msm_cs values.

 

while doing this remote system upgrade i never used the watch dog timer, if this is the problem can you provide the information regarding how to enable and use the watchdog for reconfiguration success.

 

Regards,

Shiva.

JohnT_Intel
Employee
207 Views

Hi,

 

May I know if you performed a write to offset to read the status of the application 1 or applicatoin 2? You need to trigger offset 2 before reading offset 4(bit 0 of offset 2), 5(bit 1 of offset 2) or 6 (bit 2 of offset 2).

Shiva
Beginner
207 Views

Hi,

 

Thanks for the above information provided.

 

i did it by triggering the 0th bit of offset 2 waited till busy state and read the [16:13] bits of offset 4.

 

if i do the above process by loading the pof file which is going to CFM0 and CFM1/CFM2, Before the reconfiguration triggered i am able to read "0010" (Image 0 is being loaded) and after triggering the reconfiguration "0100"(Image 1 is being loaded). which is working fine.

 

But if i do same process by sending the rpd data, Before the reconfiguration triggered i am able to read the "0010" (Image 0 is being loaded) and after triggering the reconfiguration "0101"(Image 0 is being loaded after a revert in application image happens). Can you provide the information like how to fix this issue.

 

Is it because of the way we are writing the data into onchip flash memory?

 

I am writing the data by collecting first 8 bits to LSB[7:0] then next 8 bits to [15:8] then [23:16] and [31:24] i.e..,[31,30................3,2,1,0].

 

Regards,

Shiva.

 

JohnT_Intel
Employee
207 Views

Hi,

 

May I know how do you generate the rpd file? How do you compare the flash content to be correct? Are you able to share with me the rpd file and the read out file from the flash?

 

Could you also try to use Quartus Programmer to examine the flash content?

Shiva
Beginner
207 Views

Hi,

 

I am generating the rpd file by going through convert programming files -> internal configuration(mode) -> .pof(programming file type) -> file name -> selecting 1.create memory map file 2.create config data RPD -> Under input file to convert adding the sof file two times, and then selecting the Generate option.

 

After this the tool is generating the .map, .pof, .rpd(combined), cfm0_auto_rpd, cfm1_auto_rpd, ufm_auto_rpd files. From these files we are sending the cfm1_auto_rpd file to onchip flash memory.

 

After writing the rpd file data we are reading the data from onchip flash. This data is matching with the original rpd file data.

 

Please find the following attachment of rpd file and read_out_rpd file.

 

Regards,

Shiva.

JohnT_Intel
Employee
207 Views

Hi,

 

Are you writing the combined rpd file or the split rpd file? Could you provide the detail on the step you used?

Shiva
Beginner
207 Views

Hi,

 

After clinking the generate in convert programming file the tool is generating the Combined, CFM1, CFM0, UFM rpd files, In this i am writing the CFM1 file

(already splitted rpd file) to onchip flash memory.

 

while generating the rpd file the SOF file in page_0 is the factory image and the SOF file in the page_1 is Application image, so after generating the rpd file i am sending the CFM1 rpd file (Application image) to onchip flash memory.

 

Regards,

shiva.

JohnT_Intel
Employee
207 Views

Hi,

 

Could you share with me the rpd file you use and the rpd file that you read out from the on chip flash memory?

Shiva
Beginner
90 Views

Hi,

 

Please find the following attachment of both RPD files.

 

Regards,

Shiva.

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