Intel® FPGA University Program
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Memory Blocks

Altera_Forum
Honored Contributor II
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Hello Everyone, 

 

I created a RAM (Port 1 memory) using MegaWizard. Afterwards, I instantiated that module into a new verilog file. 

 

I have been asked to use toggle switches SW(7-0) to input a byte of data into RAM location identified by a 5-bit address specified with toggle switches SW (15-11). Use SW17 as write signal and use KEY0 as clock input.  

 

I am also supposed to display address value, data being input to memory and data being read out of the memory on 7-segment display <-- this part I dont know how to do. 

 

Please help
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Altera_Forum
Honored Contributor II
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Port out address bus and input them to a seven segment decoder. The output of seven segment decoder can display memory addresses as HEX digital on seven segment display. 

 

You can apply the same configuration to memory inputs and outputs.
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Altera_Forum
Honored Contributor II
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sorry, I need 4 posts

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