Intel® FPGA University Program
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Output File is the same as the Input File Lite Edition 21.1

Nadavb
Beginner
258 Views

Hello

I have installed Rev 21.1 and when running simulation Output Input Files are the same. 

In Rev 16.1 all good.

I would appreciate any help.

 

Nadavb_0-1649664090632.png

 

0 Kudos
4 Replies
ShengN_Intel
Employee
234 Views

Hi,


Make sure you are using Max II device family and recompile again before creating vector waveform file (vwf). Should be able to see the output after making changes to device family.


Best Regards,

Sheng

p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.


Nadavb
Beginner
218 Views

Hello Sheng

With Max II recompile I get the same problem.

Thanks 

ShengN_Intel
Employee
209 Views

Hi,

 

Select Auto device selected by the Fitter in Target device window for MAX II family then recompile and recreate vwf file. Next run Timing Simulation in vwf. I think you are selecting MAX II device which is not supported for vwf. Below attached a sample file for your reference.

ShengN_Intel_0-1650188786797.png

 

Best Regards,

Sheng

p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.

 

Nadavb
Beginner
188 Views
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