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Valued Contributor III
928 Views

PLEASE HELP!!! SimulaTION ERRORS??!?

Hello. I am trying to simulate my file, but I keep receiving error messages no matter what. 

I am attempting to design a synchronous counter that outputs the the sequence 4-7-3-5-2. 

I am completely new to CPLDs and VHDL....but I have to complete this project for school. 

 

Here are the error messages I am getting: 

 

Error: Simulation results from C:/altera/72sp2/quartus/Adam/syncount/db/syncount.sim.cvwf (0 ps to 100.0 us) do not match expected results from vector source file C:/altera/72sp2/quartus/Adam/syncount/syncount.vwf 

Error: Logic level(s) do not match expected level(s) 

Error: Logic level 100 does not match expected logic level XXX for node "q" at time 0 ps 

Error: Logic level X does not match expected logic level U for node "state" at time 0 ps 

 

Can someone help me out ?
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Valued Contributor III
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The error messages are simply cause you enabled the check output option in simulation settings (Tab verification) without providing useful data to compare.

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Valued Contributor III
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Thank you~ but now it says Error: Can't continue timing simulation because delay annotation information for design is missing. I am not even sure what this is or how to enter this information. Any pointers? 

 

Thank you!
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Valued Contributor III
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Ok well I got around that problem by running the Fitter and then the Timing Analyzer. The new problem is that the simulation is not interpreting the state signals of my vhdl code. I wrote the code so that q will equal one of five states that run in sequence. The simulator fails to recognize this. While creating the Vector Waveform file, I had to use Node finder. In Node Finder, the state signals are not .....in an acceptable form for the simulator I assume? Because when I drag them over to the waveform file and click "Start Simulation," I keep getting warnings like: 

 

warning: signal state does not exist in waveform. ignore comparison settings on this signal. 

warning: ignored node in vector source file. can't find corresponding node name "state.s0" in design. 

warning: ignored node in vector source file. can't find corresponding node name "state.s1" in design. 

warning: ignored node in vector source file. can't find corresponding node name "state.s2" in design. 

warning: ignored node in vector source file. can't find corresponding node name "state.s3" in design. 

warning: ignored node in vector source file. can't find corresponding node name "state.s4" in design. 

warning: ignored node in vector source file. can't find corresponding node name "state~0" in design. 

 

 

I am pretty sure it is something very simple that I overlooked or didn't realize, but can someone help me out?
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