Hi, i am working on the porject to analyze the power cosumption of my networking switch. But the PowerPlay Analyzer just gave me some funny results, which i cannot explain.For instance, my switch consists of 4 MUX and 16 FIFOs. The total dynamic power of the switch is about 28.5mW. On the other hand, i also meansure the power consumption for each individual componenets, MUX and FIFO. Supposedly, 4*power(one MUX)+16*power(one FIFO) = power(whole switch). But the calculated power from each component is much larger than the power of the switch. Did anyone here ever work with the PowerPlay Analyzer or have any idea how the analyzer works to calculate the power? Thanks.
Hi,I have occasionally used the powerplay with no surprises. I used the default toggle rate(I believe it was 12.5%). How did you get power of each of muxes or fifos. If you recompile your design with just one mux then it doesn't add up because the whole FPGA is configured and functional in each case. You can't break it up like that according to my experience and version. Your figure of few mW seems unrealistic to me (For a full stratix II I get 6W). kaz
so you mean every time when you compile/configure your design, you acutally run up the whole FPGA resources in the device. I think it will explain why i have such funny results.I simulate my design with a waveform in about 5ms, then the generated saf file is used to check the power with PowerPlay Analyzer. That is what i got about 28mW as the dynamic power. do you have any comments in my operation? i really need your help to figure out the problems in my way to analyze the power of my design since my paper is due on Dec. 05. Thanks.
Hi,I didn't say that resource is used in all cases but the fpga draws power and all the configuration circuitry is on. The main info that the power analyser wants is the toggle rate. a simulation result(SAF) is best according to altera. Alternatively use manual toggle rate(average). This is explained below(from an altera doc). Try and play with toggle rate between 0 and 100. if you get funny results then may be the version you have is not well... kaz from altera doc: Toggle percentage is the average percentage of logic toggling on each clock cycle. The toggle percentage ranges from 0 to 100%. Typically, the toggle percentage is 12.5%, which is the toggle percentage of a 16-bit counter. To ensure you do not underestimate the toggle percentage, you can use a higher toggle percentage. Most logic toggles infrequently, and therefore toggle rates of <50% are more realistic. For example, a FF with its input tied to VCC has a toggle rate of 100% because its output is changing logic states on every clock cycle. For a 4 bit counter, the first FF with least significant bit (LSB) output cout0 has a toggle rate of 100% because the signal toggles on every clock cycle. The toggle rate for the second FF with output cout1 is 50% since the signal only toggles on every two clock cycles.Consequently, the toggle rate for the third FF with output cout2 and fourth FF with output cout3 are 25% and 12.5%, respectively. Therefore, the average toggle percentage for a 4-bit counter is (100 + 50 + 25 + 12.5)/4 = 46.875%.