Intel® FPGA University Program
University Program Material, Education Boards, and Laboratory Exercises
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
1238 Discussions

Problem : University VWF

Altera_Forum
Honored Contributor II
‎01-22-2016 10:09 PM
2,125 Views

Hello everyone. I'll start by saying that my english sure it's not the best, i apologise for that; but i'll try anyway to be as clear as possibile , so i'm trying to simulate this fives clockS but i'm getting this error :( 

 

1st i've create a new verefication / debbugin files which is ==> University Program VWF , and i've added my In/Out and i get the following error ! 

 

http://www.alteraforum.com/forum/attachment.php?attachmentid=11728&stc=1  

 

Please help me as soon as possible thanks in advance.
Preview file
197 KB
0 Kudos

Link Copied

0 Replies
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.