Intel® FPGA University Program
University Program Material, Education Boards, and Laboratory Exercises
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Problem with simulation: top level entity name and revision name must match.

Honored Contributor II

When I try to use the simulator (from University Program vwf), it works fine if the top level entity and project name and revision name match. But if revision name, top level entity name and project name don't match I get something like the following in the "Simulation Flow" window. (in this case FirstLecture is the project name and Example7 is the top level entity and revision name). Is there a way to run the simulation without making the names all the same? 

>> vsim -c -do 

PID = 6168 

Reading C:/altera/13.0/modelsim_ase/tcl/vsim/pref.tcl  

# 10.1d 

# do  

# ** Warning: (vlib-34) Library already exists at "work". 


# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012 

# ** Error: (vlog-7) Failed to open design unit file "Example7.vo" in read mode. 


# No such file or directory. (errno = ENOENT) 

# ** Error: c:/altera/13.0/modelsim_ase/win32aloem/vlog failed. 

# Executing ONERROR command at macro ./ line 3
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