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Altera_Forum
Honored Contributor I
1,193 Views

SDRAM on DE2

Hi friends: 

I come up with a problem on DE2 board.In the SOPC builder,I set the clock of both SDRAM and CPU 50Mhz,when I download the software in Nios,it said "Verify failed between address 0x800000 and 0x8062B3,Leaving target processor paused",then I change the clock of CPU to 100Mhz,and the problem was solved,do you know why this happened?
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15 Replies
Altera_Forum
Honored Contributor I
34 Views

Hi. 

I'm not sure but, check the SDRAM controller code, also you need to delay the SDRAM clock -3ns.
Altera_Forum
Honored Contributor I
34 Views

Hello, I have been battling with the SDRAM problem for some time, but I cannot find a solution. I have tried to use 100MHz and 50MHz clock, both with and without the delay and I still get the verified failed error. Could there be anything else that I am missing? Thanks a lot for help, because this is driving me crazy!

Altera_Forum
Honored Contributor I
34 Views

 

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I think your pin connection or timing are setting a wrong value. Please checking the SDRAM timing in SOPC builder and check pin connection on your TOP file. Maybe you can compare with the example of DE2_70_NET project.
Altera_Forum
Honored Contributor I
34 Views

I guess u need to add pll to counter the skew and other timing issues between the sdram controller clock and the clock provided to the sdram chip..

Altera_Forum
Honored Contributor I
34 Views

Can you post the procedure you are following. That might help us track down the problem faster.

Altera_Forum
Honored Contributor I
34 Views

I'm having exactly the same problem as swordflyer - with Quartus 9.0 

I hope there is some insight here somewhere.
Altera_Forum
Honored Contributor I
34 Views

Here is the link, 

 

university.altera.com/materials/comp_org/tutorials 

 

Please confirm.
Altera_Forum
Honored Contributor I
34 Views

Thanks - I ended up adding a second clock to the PLL, going straight through, 

as suggested by the tutorial. That worked. Interesting though that a few years 

ago you did not need to send the CPU clock through the PLL. 

 

Now if I can get the Terasic ISP1362 (USB) IP to work with Quartus 9.0/9.1.
Altera_Forum
Honored Contributor I
34 Views

I've a very similar problem, and I cannot communicate with the sdram, 

(nor to download the program into it of course) 

 

However the problem is limited to the usage of the Nios in the version standard or fast, while when i use the "e" version everything works properly.  

 

I found this unusual behavior both on DE1 and on DE2 board. 

I'm using Quartus 9.1 ad the sdram clock is controlled by a -3ns PLL. 

 

 

Someone has been able to communicate with the SDRAM using NiosII/s or NiosII/f ?
Altera_Forum
Honored Contributor I
34 Views

when I added the through-clock signal to the PLL we were able to get it working 

(and I've always used the f version of the cpu). I'm not sure what your situation 

is.
Altera_Forum
Honored Contributor I
34 Views

I'm stack with this sdram controller:/ Did everything what I found in this forum and still it doesn't work:/

Altera_Forum
Honored Contributor I
34 Views

Altera_Forum
Honored Contributor I
34 Views

Altera_Forum
Honored Contributor I
34 Views

I found the solution. I had to use 2 clock signals from pll. One for sdram and one for fpga. Then it works.

Altera_Forum
Honored Contributor I
34 Views

this problem is generic for using sdram~! 

 

I think a phase shift between SDRAM Controller's clock and SDRAM Chip's clock! 

 

I setup phaseshift is -3000(dg)!
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