Hello,Take a look at this reference. http://www.cs.columbia.edu/~sedwards/classes/2011/4840/video.pdf (http://www.cs.columbia.edu/~sedwards/classes/2011/4840/video.pdf) Please pay attention to Hsync, Vsync and Blank polarity. If the polarity is wrong the problem usually looks like this. Did you use Signal Tap for debugging? Good luck,
I agree with Reuven. Also if you are driving and LCD panel, the timing may be more critical in the system than if you were driving a CRT.http://www.xfree86.org/3.3.6/config7.html has some video timing standards to look at. Old CRT's were pretty forgiving on this, but LCD's can be pretty tight on the requirement. You usually can get away with a different pixel clock (IE 25 MHz instead of 25.175) but the sync timings have to be pretty close, so you end up eating the front porch/back porch time to make it work. Pete
Hello,Thanks for the reply and the manual, it helps me a lot ! I think the polarity is correct because I was able to run the DE2_TV example from the DE2 CD. The monitor I used was the old CRT and the clock I had tried were 25MHz and 25.2MHz. Other than that, the timing I used was: // Horizontal Parameter ( Pixel ) parameter H_SYNC_CYC = 96; parameter H_SYNC_BACK = 48; parameter H_SYNC_ACT = 640; parameter H_SYNC_FRONT = 16; parameter H_SYNC_TOTAL = 800; // Virtical parameter ( Line ) parameter V_SYNC_CYC = 2; parameter V_SYNC_BACK = 32; parameter V_SYNC_ACT = 480; parameter V_SYNC_FRONT = 11; parameter V_SYNC_TOTAL = 525; The problem seem like the monitor did not turn on after downloading the program. I afraid my code got problem. I hope there got any simple VGA verilog code example that I can refer. Thanks ! Best Regards, TWK
Hello,If the monitor turns off when you load your design to the FPGA the problem could be the HS & VS signals supplied to the monitor and not the data R, G & B. I would connect the signal TAP to these two lines that go out of the FPGA to the monitor. The signal TAP sampling clock should be the 25MHz clock. In the signal Tap you can check these signals and for how many clocks they are in high and low state? It will be helpful if you can post here a picture of the signal TAP result. Good Luck!
Hi,Thanks for the suggestion ! After using SignalTap debugging, I found out that VGA_VS never low (show in list file). I not sure my V_Sync Generator correct or not. Here is the code: always @(posedge iCLK, posedge iRST) begin if (iRST) begin V_Cont <= 0; VGA_VS <= 1'b0; end else begin // When H_Sync Re-start if (H_Cont==H_SYNC_TOTAL-1) // V_Sync Counter if (V_Cont < V_SYNC_TOTAL-1) V_Cont <= V_Cont+1'b1; else V_Cont <= 0; // V_Sync Generator if (V_Cont < V_SYNC_CYC) VGA_VS <= 1'b0; else VGA_VS <= 1'b1; end end Best regards, TWK
Sorry, got some correction here. I just found out that VGA_VS actually got low when the conditions are H_Cont==H_SYNC_TOTAL-1 where H_SYNC_TOTAL=800 and V_cont counter also must be 0 or 1. V_cont counter will only count up after every 800 H_cont count. Is my VS and HS generator correct for this case?Best regard, TWK
Hi again,I do not see any problem with the code you wrote. Maybe the next step is to look with a scope at the 5 signals supplied to the monitor: Red, Green, Blue, HS & VS. Compare this signals running your project vs. running DE2_TV example. BR,