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MDavi68
Novice
310 Views

Why fpga_crossgen is given an error "aocl-clang-9: error: cannot specify -o when generating multiple output file" using Version 19.3?

Hello,

I am testing fpga_crossgen to develop libraries from *.cpp to OpenCL. I am following the example "OpenCL Matrix Multiplication Hierarchical Library" , i++ compilation is ok, but in the step:

fpga_crossgen --target hls device/lib/dot_prod.cpp -o bin/test/dot_prod.o

 

The error is:

aocl-clang-9: error: cannot specify -o when generating multiple output file.

 

I am using Intel HLS compiler 19.3 with CentOS Linux release 7.7.

 

Thanks in advance.

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2 Replies
MEIYAN_L_Intel
Employee
160 Views

Hi,

Since you are using the OpenCL source code to create library object, according to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/opencl-sdk/aocl_programm... in chapter 10.1.1.1, you may need to use command as below:

fpga_crossgen --target target_HLD_tool [-o ] 

 

Thanks

jomarm10
Beginner
82 Views

Hi I am facing the same problem when attempting to compile with fpga_crossgen script.

When I runn following command
 >> fpga_crossgen -v --target hls foo.cpp -o foo.o

I get 
>> Creating HLS Library object from foo.cpp for foo.o
comand : i++ /home/intel/intelFPGA_pro/19.3/hls/linux64/bin/../../gcc -c --createlibobject foo.cpp -o foo.o
aocl-clang-9: error: cannot specify -o when generating multiple output files
HLS Testbench parse FAILED

After checking the command the command the script triggers, to check the full command and, after passing the verbose option and setting the part of the device we have, I still get the same message when launching the command (as I expected)

$ i++ /home/intel/intelFPGA_pro/19.3/hls/linux64/bin/../../gcc -c -v -march="1SM21BHU2F53E1VG" --createlibobject foo.cpp -o foo.o

Target FPGA part name: 1SM21BHU2F53E1VG
Target FPGA family name: Stratix10
Target FPGA speed grade: -1
Analyzing foo.cpp for testbench generation
aocl-clang-9: error: cannot specify -o when generating multiple output files
HLS Testbench parse FAILED.

What am I doing wrong?
Am I missing something?

 

I am running quartusPrime_pro 19.3 on a centos 7.2.1511
Before running the fpga_crossgen script I perform following actions:
  - set the environment variables for Quartus,  and
  - source the script: 
         ​   .../intelFPGA_pro/19.3/hls/init_hls.sh

With following output of the script
$ source /home/intel/intelFPGA_pro/19.3/hls/init_hls.sh
[i] INFO:
Taking this scripts' directory
'/home/intel/intelFPGA_pro/19.3/hls'
as the root of the Intel(r) HLS Compiler installation.

[i] INFO:
Adding directory
'/home/intel/intelFPGA_pro/19.3/hls/bin'
to environment variable PATH

[i] INFO:
Adding directory
'/home/intel/intelFPGA_pro/19.3/hls/host/linux64/lib'
to environment variable LD_LIBRARY_PATH

[i] INFO:
Quartus is available through your environment:
${QUARTUS_ROOTDIR_OVERRIDE} ->
/home/intel/intelFPGA_pro/19.3/quartus

[i] INFO:
Prioritizing directory
'/home/intel/intelFPGA_pro/19.3/quartus/bin'
in environment variable PATH

[i] INFO:
ModelSim is available on your PATH:
'/home/intel/intelFPGA_pro/19.3/modelsim_ase/bin/vsim'

[i] INFO:
ModelSim simulator version:
Model Technology ModelSim ALTERA STARTER EDITION vsim 2019.2 Simulator 2019.04 Apr 17 2019

[i] INFO:
Found GCC Tool Chain in your installation directory.

[i] INFO:
Adding directory
'/home/intel/intelFPGA_pro/19.3/hls/gcc/bin'
to environment variable PATH

[i] INFO:
Adding directory
'/home/intel/intelFPGA_pro/19.3/hls/gcc/lib64'
to environment variable LD_LIBRARY_PATH

[i] INFO:
Cleaning up variables...