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Why is the FPGA Monitor Program Editor (from the UPDS) disabled/not working?

PKoor
Beginner
405 Views

Freshly installed on Windows10 with Quartus Prime 18.1, the intel FPGA Monitor Program built-in Editor (and "Project Files") are disabled from the "Windows" menu (grayed-out). The symptoms are similar to other posts, e.g. "Altera monitor program text editor not appearing". What is wrong? Is it maybe a Java problem? When I first started the Monitor program, I got a Java firewall warning (but said "run anyway").

Thanks.

-- Paul.

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2 Replies
EBERLAZARE_I_Intel
237 Views

Hi Paul,

 

I apologize for the late response, as I just got the notification.

 

The editor will be disabled during the debug session, and re-enabled when the debug session is exited

 

The source level debugging feature of the Monitor Program is a beta feature in the current release. The feature can be enabled and disabled at any point by going to the Edit menu and selecting Edit > Enable Source Level Debugging, or Edit > Disable Source Level Debugging, depending on whether the feature is currently disabled or enabled respectively.

 

Regards.

EBERLAZARE_I_Intel
237 Views

Hi,

 

Do you have any follow up from your side?

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