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Altera_Forum
Honored Contributor I
1,110 Views

a DE1-SOC + VIP (TPG+VCO) does synthesize but does not simulate

Hi ! 

 

I've been designing a very simple design. 

This is a test, inspired from Terasic's video demo to see how the clock and reset networks are set. 

This is a TPG connected to the video out controller + reset and clocks: nothing complex at all. 

 

Qsys + Logical + physical synthesis all work fine. 

With Quartus, I'm trying to do a RTL level synthesis but the compilation process (Modelsim) 

stops with an error signaling a missing alt_vip_common_pkg package. 

I checked in the "video_simple_run_msim_rtl_vhdl.do" (the "do" file), 

and there is no trace of the compilation of this alt_vip_common_pkg package. 

 

The exact error message is:  

"(vlog-13006) Could not find the package (alt_vip_common_pkg)." 

 

So my questions are:  

 

"How is it possible that Qsys could generate an incorrect do file 

but generated all good for synthesis ?" 

 

Or, "would there be a missing library link somewhere to access these 

crypted IPs from Altera ?" 

 

If anyone has experienced this, please just leave an answer. 

 

Many thanks, 

Pierre 

PS: I'm not a beginner, I've been working with Xilinx' tools 

for 15 years. But, right, I'm new to Altera's world. This is why a so 

simple design error frustrates me a lot :-)
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9 Replies
Altera_Forum
Honored Contributor I
34 Views

 

--- Quote Start ---  

 

The exact error message is: 

"(vlog-13006) Could not find the package (alt_vip_common_pkg)." 

 

--- Quote End ---  

 

Search the .do file for alt_vip_common_pkg. Where is it? 

 

If its only in the vsim -L list of libraries, then its likely due to an oversight of the .do script generator. Modify the script and delete that entry. 

 

You could also try adding a vlib statement to create alt_vip_common_pkg as an empty library. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
34 Views

Thank you very much Dave. 

 

Of course, I immediately had a look to all these files for simulation. 

 

In the .do file, there was no explicit ref to any alt_vip_common_pkg library to add or file to compile. 

 

The compilation error comes from a VHDL file named "alt_vip_cvo_core.sv" 

at the line 77: it contains a "import alt_vip_common_pkg::*;" 

 

The file alt_vip_common_pkg.sv does exists in the same directory than 

the alt_vip_cvo_core.sv, but it is not included in the .do file for 

compilation. 

 

I added it manually and reran the compilation: it fails when compiling 

alt_vip_common_pgk.sv because the file is crypted. By the way, this was the 

opportunity for me to discover this. 

 

So, I suppose that there should be somewhere a 

precompiled version of all these Altera's proprietary (and crypted) files. 

And I searched everywhere ... (but not in the whole doc yet). 

 

Unfortunately, there are no "modelsim" (I mean *.qdb) files about any VIP 

unit under the Quartus 14.1 installation directory. 

 

I suppose these precompiled libs for Modelsim must be obtained 

somewhere: probably Altera ... 

 

I will ask Terasic (the DE1-Soc board makers) how they simulated there  

VIP demo when debugging it. For sure they did it ! 

 

I'll keep the community informed when I have fresh news. 

 

If you have any suggestions, do not hesitate. I think I am stuck ... 

 

Kind regards, 

Pierre
Altera_Forum
Honored Contributor I
34 Views

Of course I tried to create an empty lib alt_vip_common_pkg: the same error occurs 

I also tried to remove the line 77 to see what will happen later: an other error occurs later 

 

There is really some useful stuff in that lib :-)))) 

 

Pierre
Altera_Forum
Honored Contributor I
34 Views

I'd recommend filing a Service Request directly with Altera. 

 

While you are waiting, you could also try an older version of Quartus, eg., look at whatever ships with your Terasic hardware (open the .qsf to see what the last version of Quartus used was), and use that version. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
34 Views

You are totally right, the Terasic's ref design has been build with a 13.1 version, and I'm using a 14.1 version ... 

I'll try this tomorrow, to check. 

If it does not work, I'll contact Altera. 

Many thanks for your advices, 

Pierre 

 

PS: the .qsf contents are: 

set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13 

set_global_assignment -name LAST_QUARTUS_VERSION 13.1
Altera_Forum
Honored Contributor I
34 Views

I did a test with the 13.1 version. 

Now it compiles. 

We can consider this thread as closed now. 

Many thanks to Dave, 

Pierre
Altera_Forum
Honored Contributor I
34 Views

 

--- Quote Start ---  

I did a test with the 13.1 version. Now it compiles. 

 

--- Quote End ---  

 

Ok, that is good. 

 

Even though you have confirmed it works under 13.1, it would be nice to get it to work under 14.1, since there may be bugs in 13.1 that you have yet to stumble upon :) 

 

I'd recommend saving the working version (.qar file) and then re-open the project in 14.1. Perform whatever step is needed to upgrade the IP, and then try simulating again. 

 

If that sequence fails, open a Service Request and send the 13.1 .qar file and notes as to the upgrade steps you performed and ask Altera why it fails. 

 

Bugs in the Altera tools cannot be fixed without demonstrations of those bugs, so it is useful to provide feedback to Altera. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
34 Views

Hi Dave, 

 

You are absolutely right. 

 

I appreciate very much Altera's tools that allowed me to do in 2 weeks what I have 

been unable to do with Xilinx for months. I started "from scratch". 

So I have now a very positive attitude for Altera. 

I also recommended to my colleagues (Université de Bretagne Sud, UBS, France) to switch  

from Xilinx to Altera for their future designs. 

 

Considering the problem I experienced, I must now admit that all works fine with 14.1 

I probably made something wrong (but what ?) within the 1rst design. 

The main difference is that I was using the "version II" of the TPG and the VCO, rather 

than the original ones.  

I confirm that, with all versions of these IPS, logical & physical synthesis ALWAYS WORKED. 

Only with version II, I had simulation troubles (compilation libraries).  

But, I'm still a beginner with Altera and I must continue to learn more :-) 

The "probability of mistakes" is today far more on my side than on Altera's. 

 

So, what's next now ? 

 

I'll keep an eye on reproducible problems, for sure. And I will forward relevant data (.qar) 

to Altera when needed. 

 

Many thanks to you and to all the contributors of these very helping threads, 

Pierre
Altera_Forum
Honored Contributor I
34 Views

Hi Pierre, 

 

I'm glad to hear you got your design working. Thanks for posting feedback on how you solved your issue. Hopefully it'll help the next person :) 

 

 

--- Quote Start ---  

 

Many thanks to you and to all the contributors of these very helping threads 

 

--- Quote End ---  

 

You're welcome. 

 

Cheers, 

Dave
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