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Altera_Forum
Honored Contributor I
736 Views

about the Reset_Delay.v in DE2_D5M

The following is excerpted from Reset_Delay.v of the project de2-d5m  

always@(posedge iCLK or negedge iRST)  

begin  

if(!iRST)  

begin  

Cont <= 0;  

oRST_0 <= 0;  

oRST_1 <= 0;  

oRST_2 <= 0;  

end  

else  

begin  

if(Cont!=32'h13FFFFF) Cont <= Cont+1;  

if(Cont>=32'h1FFFFF) oRST_0 <= 1;  

if(Cont>=32'h2FFFFF) oRST_1 <= 1;  

if(Cont>=32'h13FFFFF) oRST_2 <= 1;  

end  

end  

I don't understand why it sets cont as 32'h1FFFFF&#65292;32'h2FFFFF&#65292;2'h13FFFFF. 

Can anybody help me?
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4 Replies
Altera_Forum
Honored Contributor I
31 Views

This is module Reset_Delay in DE2_TV project: 

 

module Reset_Delay(iCLK,iRST,oRST_0,oRST_1,oRST_2); 

input iCLK; 

input iRST; 

output reg oRST_0; 

output reg oRST_1; 

output reg oRST_2; 

 

reg [21:0] Cont; 

 

always@(posedge iCLK or negedge iRST) 

begin 

if(!iRST) 

begin 

Cont <= 0; 

oRST_0 <= 0; 

oRST_1 <= 0; 

oRST_2 <= 0; 

end 

else 

begin 

if(Cont!=22'h3FFFFF) 

Cont <= Cont+1; 

if(Cont>=22'h1FFFFF) 

oRST_0 <= 1; 

if(Cont>=22'h2FFFFF) 

oRST_1 <= 1; 

if(Cont>=22'h3FFFFF) 

oRST_2 <= 1; 

end 

end 

endmodule 

 

I can't understand this module too, why do they get these numbers? Pls help me. Thanks
Altera_Forum
Honored Contributor I
31 Views

The module Reset_Delay.v in DE2_D5M is generating 3 reset signals. They are separted in time. This is to allow different parts of the DE2_D5M system to be reset one after another. 

 

The delay times for the reset are only arbitrary times in order to allow different modules / external peripherals to be reset in sequence. The time is however still below 1 sec. 

 

Hope this helps.
Altera_Forum
Honored Contributor I
31 Views

 

--- Quote Start ---  

The module Reset_Delay.v in DE2_D5M is generating 3 reset signals. They are separted in time. This is to allow different parts of the DE2_D5M system to be reset one after another. 

 

The delay times for the reset are only arbitrary times in order to allow different modules / external peripherals to be reset in sequence. The time is however still below 1 sec. 

 

Hope this helps. 

--- Quote End ---  

 

 

what i would like to know is why they use 1FFFF,2FFFFF and 3FFFF with a clock 50 MHz, i think that this are for the following time 42ms,63ms and 84 ms i have tried to calculate this time for a bust write in SDRAM, but don't have succes. 

 

How are caculated this time ?
Altera_Forum
Honored Contributor I
31 Views

Hi, I have been working with the TRDB-D5M Terasic Camera module. I have noticed that this sample code also has got the Reset_Delay which generates 3 reset signals. I understand that these delays have been chosen randomly, yes well within 1sec. If you look at TRDB-D5M code, RST_1 is 42ms, RST_3 is 63ms and RST_2 is 0.36 sec. These are fed to various modules. This is believe is to have an orderly turnining on of each of the modules. Also, a certain start up time needs to provided before the Camera data can be read in this case, since some initial time is used for Camera registers to be configured.  

 

Once these elapsed times are over, each of the modules (doing various operations) are in operation. This is my understanding really.. :rolleyes:
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