basic questions

[Altera_Forum]

Hi everyone, 

 I'm having trouble with the code I posted below. I'm trying to design an ALU and am having conceptual problems.  Seems like for the case when sel is "1000" I get errors saying I need to use :=  I'm actually very confused about the difference between <= and := . Could someone please explain the difference?  In any case neither <= or := works with my code it seems.  Furthermore could someone explain to me the difference between std_logic_vectors and signed/unsigned numbers?  Also for the case when sel is "0010" is it okay for me to make the following comparison: unsigned(temp) > (2**WIDTH)-1  Thank you  --------------------------------------------------  library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;   entity alu_ns is   generic ( WIDTH : positive := 16 );   port ( input1 : in std_logic_vector(WIDTH-1 downto 0); input2 : in std_logic_vector(WIDTH-1 downto 0); sel : in std_logic_vector(3 downto 0); output : out std_logic_vector(WIDTH-1 downto 0); overflow : out std_logic );   end alu_ns;   architecture alu_arch of alu_ns is begin    process(input1, input2, sel)  variable temp : std_logic_vector(WIDTH-1 downto 0);  --variable temp_mult: signed(2*WIDTH-1 downto 0);  begin    overflow <= '0';    case sel is    when "0000" =>  temp := std_logic_vector(resize(unsigned(input1), width + 1)+resize(unsigned(input2), width + 1));  output <= temp(width downto 0);  overflow <= temp(WIDTH);    when "0001" =>  temp := std_logic_vector(signed(input1)-signed(input2));    when "0010" =>  temp := std_logic_vector(signed(input1)*signed(input2));  if (unsigned(temp) > (2**WIDTH)-1) then  overflow <= '1';  end if;    when "0011" =>  temp := std_logic_vector(input1 and input2);    when "0100" =>  temp := std_logic_vector(input1 or input2);    when "0101" =>  temp := std_logic_vector(input1 xor input2);    when "0110" =>  temp := std_logic_vector(input1 nor input2);    when "0111" =>  temp := std_logic_vector(not input1);    when "1000" =>  --temp <= input1 sll 1;  temp <= input1(WIDTH-2 downto 0) & "0";    when "1001" =>  temp := '0' & input1(WIDTH-1 downto 0);    when "1010" =>  temp := input1(width/2 downto 0) & input1(width-1 downto 0);    when "1011" =>  for i in 0 to WIDTH-1 loop  temp(i) := input1((width-1)-i);  end loop;    when others =>  temp := (others => '0');    end case;    output <= temp(width-1 downto 0);    end process;    end alu_arch;

[Altera_Forum]

<= is for assigning a signal 

:= is for assigning a variable.  Signals and variables behave differently. Variables are assigned immediately whilst signals are assigned when a wait occurs or the process suspends. I highly recommend you dont use variables until you unstand the implications of their behaviour. There is nothing you need a variable for - you can do everything you need for synthesis with signals, and it wont give you odd behaviour.  Std_logic_vectors are intended to just represent a collection of bits. Unsigned/signed types are meant to represent unsigned/signed numbers.