Refer the "1.2. Generating IP Cores (Intel Quartus Prime Pro Edition) " from link below & configure the different parameters of IP in parameter editor & then add the instance of that IP core in top module of your project & eventually perform compilation & simulation.
not yet I am still working on it,
I have tried to configure it as shown in your reference, added it to the main verilog code, but it seem that it is not detected while in eclipse.
my IPcore is very simple, it just requires clk, rst as inputs and produces a 32 bit signal (without any parameters).
my goal is just to read this output data in eclipse.
I can provide further information if needed.
"I have tried to configure it as shown in your reference, added it to the main verilog code, but it seem that it is not detected while in eclipse." you have add that *.qxp file in IP search path & instantiate that in top module manually or you can also do it by using Qsys(you have to take care about Qsys signal & Interfaces etc) as shown in below video,
Eventually refer "1.1.2. Adding IP Components to IP Catalog" from link below,
Thanks for the design details.
Actually VGA_Subsystem module is missing, while creating the custom core, it is necessary to add the respective module design file in component editor & configure the signals & interfaces as per your requirement so add the design file under 'Files' tab. In fact all the required steps are shown in attached video link(previous post) please follow the steps carefully & apply to your design.
The most important thing is, ensure that there should not be any error in your 'Messages' window.
Note: if you have any different concern please open new thread for better support.