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Altera_Forum
Honored Contributor I
712 Views

de2i-150 PCIe for production?

Hello, 

I have followed the general instructions for building and running the Yocto ecosystem on the board. For the communication between the Atom and the FPGA, there are some files under a demonstration folder on the CD, and it is quite enphasized that this API is for demonstration and test. 

It makes me think that these are not for "production" usage, as they are possibly not properly optimized for high performance usage. Hence, I think that I should write my own modules for low level communication. But it appears that they doesn't even give their source codes. 

 

What is he best way to access the PCIe for high speed communication between the Atom and the FPGA on this board? I'm not sure how is the best way to do that. 

 

Best regards
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3 Replies
Altera_Forum
Honored Contributor I
33 Views

Hello Guilherme, 

Have you had any progress since you sent this message? 

We are intending to use the PCIe communication on this board and we are interested in the subject. 

Best regards, 

Menotti
Altera_Forum
Honored Contributor I
33 Views

 

--- Quote Start ---  

Hello, 

I have followed the general instructions for building and running the Yocto ecosystem on the board. For the communication between the Atom and the FPGA, there are some files under a demonstration folder on the CD, and it is quite enphasized that this API is for demonstration and test. 

It makes me think that these are not for "production" usage, as they are possibly not properly optimized for high performance usage. Hence, I think that I should write my own modules for low level communication. But it appears that they doesn't even give their source codes. 

 

What is he best way to access the PCIe for high speed communication between the Atom and the FPGA on this board? I'm not sure how is the best way to do that. 

 

Best regards 

--- Quote End ---  

 

 

Hi Guilherme, 

 

It's true that the demo is likely not optimized, as the idea is for users to have a reference to communicate between the CPU and the FPGA.  

 

On the other hand, it doesn't necessarily indicate it's not ready for high performance usage, but it really depends on your definition. Perhaps it would be better if you have a number measured from practical result for comparison. 

 

Could you point out which part of source code is not given ? 

 

Thanks, 

 

David from Terasic
Altera_Forum
Honored Contributor I
33 Views

Ricardo, 

I haven't got much progress, because I'm envolved with a project with this board and we haven't started coding yet. 

 

Dav, 

We will need the PCIe bus for low-latency and high data exchange rate between the FPGA and the CPU. This is due to the fact that we will be working with computer vision, and we want our system to be relatively responsive. Unfortunately, I can't give any numbers since I haven't started developing yet, but it would suffice to know if the driver can support up to the maximum transfer rate, which I believe is of 250MB/s. 

 

The code that I can't find would be the driver code. The SystemCD that I can download from the terasic website only gives me an installer with the windrv stuff inside and no code to access. 

This driver seems to be made with WinDriver or something. But also it would be great to have access to the libraries source codes, not only the TERASIC_PCIE.h header, so that we could see how the communication is made in low level, and be able to personalize it. 

 

Many thanks.
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