library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity XOU is port (clk,r,dec:in std_logic;dout:out std_logic); end XOU; architecture AXOU of XOU is signal dd: std_logic_vector(7 downto 0); begin process(clk,dec,r) begin if r='1' then dout<='0';--dd<=(others=>'0');; elsif rising_edge(clk) then if dec='0' then dout<='0'; --dd<=(others=>'0'); else dout<=dd(7 downto 1)&'0'; end if; end if ; end process; end AXOU;
hi; i was wondering if u could help me with the Error (10327): VHDL error (can't determine definition of operator ""&"" -- found 0 possible definitions)
and this is the code
Hi Vicky, Hi Deddi,
In first line 18 use dout as Single bit Std_Logic zeroing dout
line 20 use the aggregate so dout is used as Std_Logic_vector(7 downto 0)
in every case this cannot work, shift register destination must be itself, line 20 dd <= dd(7downto 1)&'0'; -- (Shift left filling zero)
shift register is free running.
about error, cannot assign right side vector of 8 Std_logic element to left side single std_logic. .
For shift register, you can get easily HDL code online but for the user defined value shift register you need to use generic concept.
in this case, concatenation operation will not work since dout is single bit.