hello, can anybody tell me how to send pixels to vga monitor. my code is:
color=(((img_R[i][j] >>8 ) & 0x0000F800)+ ((img_G[i][j] >>5 ) & 0x000007E0)(((img_B[i][j] >>3 ) & 0x0000001F));
the quality of the image displayed on the monitor is very bad, any clue?
firstly, I am sending several copies to different groups of specialists of altera,
secondly, last time I was asked to change the intended group as they couldn't answer my question,
as for the details, I would provide any detail about my project if just asked, and beside this,
all my questions up to know are basic as I have just working with altera board and Iam not an expert.
I hope that clarifies a bit more for you.
and also ,if you are following, I have attached my whole project in a previous post and the function you are
asking for is a basic function of drawing a pixel in a screen, I mean there is no simpler way to do it.
so plz try to have a look on the previous posts and avoid making assumptions.
Being new FPGA user is fine. My point is people can help you better if you can be more specific in your questions asked.
For instance : can someone teach me how to use xxx function in yyy IP of zzz Intel FPGA example design ?
After some time, I finally figure out you are asking about "alt_up_video_dma_draw" NIOS2 HAL function in "Pixel Buffer DMA Controller" IP of "Intel FPGA university program DE2-115_computer" example design.
Refer to below doc to learn more about capability of DE2-115 board and its Quartus example design (DE2-115_Computer)
The detail info about each video IP block can be found in below link - video IP suite doc
You can refer to below link, goto computer organization -> download "Using HAL Device Drivers with the Monitor Program" pdf file to learn more about NIOS2 HAL function for each Intel FPGA IP
Ultimately my best advise to you is to try out the DE2-115 board, video function NIOS2 c code example design directly. You can use either NIOS2 c code or NISO2 HAL function. You can then modify and play around with the example design once you get it working first.
You can also use "Intel FPGA Monitor Program" from the University Program installer to help you build the example design.
thank you dlim, for all theses references, I will try to look at them carefully.
I promise to be more specific next times as I am gaining some experience.
I have another question and I would like you just to direct me about which group I should send it to (as I know I should open another thread.)
I want to know how to read a custom IP core output data in eclipse that I have;
1. created using a vhdl code,
2.included in my design in quartus platform designer,
3.added it in the verilog code with its connections.
my problem now is how to detect it while in eclipse (I have looked into 'system.h' file but it does not appear and I do not know how to retrieve its data in my c code). I am using DE2-115 board with quartus 18.1
I hope I have been clear