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Valued Contributor III
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please help

Hello all, Once more I came to ask help from the community. 

 

I have been trying, for the last couple of moths, to add the audio core to the DE2_NET provided project. (we do not use this board at school and even the FPGA Classes are very limited)  

 

 

I have been fighting with numerous versions and sample projects just to have a in/out of the codec instead of just the DAC Fifio from terasic.  

 

So on the DE2 project, I removed the DAC fifo (terasic) and added the Audio Core from the university program. Also added the required Development Board External Interface as specified from the audio core datasheet.  

 

but I get this error, in every version I get:  

 

Error: Can't fit fan-out of node SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 into a single clock region
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Valued Contributor III
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I think I have seen this error before. It will happen when two input clocks are on the same pll bank. (I am assuming you have the two or more PLLs in your design) 

 

If you are using the same clock for two different PLLs, try and merge the two PLLs into one. 

 

Hope this helps
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Valued Contributor III
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I See , I do have two, the audo core adds one to the design. I will try that. I'll post what ever response I get

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Valued Contributor III
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Yeah. No That did not help. 

 

I actually started the project again, in a different version 7.2.  

and on version 7.2 when I add the audio core it does not add another PLL. (I'm quite fuzzy on which PLL is being used, as I do not see any on SOPC) but on the top file on this new version, I only have the previous described pll.  

 

if you have anything in mind I'm all ears. 

 

I appreciate all and any help 

 

Thanks 

Gabriel
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Valued Contributor III
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It looks like your SOPC project is driven by your PLL. If I understand right, the audio core is in SOPC also. 

 

Here are a few things to try: 

 

Running your system at 50MHz - don't use a PLL to drive your SOPC system and don't use one external to your SOPC system. 

 

If this does not suit your needs, try using the 27MHz clock for your system's PLL. You will still need to bring the 50MHz clock in from the pin directly to your SOPC system. 

 

I hope this helps out.
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