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hi.
i just got a piece of DE2 board,there is a question when i do the exercise follow the <Quatus II Introduction Using Verilog Design>, if i use the JTAG mode to programming and configure ,it's ok, at the AS mode ,i do like the follw steps: 1.assignments > device > device and pin options > configuration >chose EPCS16 > compile 2.tools > programmer > make sure the hardware setup is usb_blaster and the mode is active serial programming,add the .pof file ,check program/configure, > start 3. i turn off the power , check the run/prog switch back to run site,then turn on the power,but the board doesn't look like work normal . 4. i have try to use the "conver programming file"the generate the .pof file by the .sof file. then , use this file do it again,it works. i don't why? all steps are follw the doc.my quartus II is 9.1 web edition .Link Copied
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at the forum sb.
sad it's a bug of version 9.1. i haven' got the patch 0.63 to test.- Mark as New
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Simply update to 9.1 SP1. It's available for free.
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o , thanks ,i will try to use the sp1 version
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I had the same problem. My solution was to convert the .sof to .pof from File->Convert Programming files
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I had a similar problem at GXII PCIe card, the solution is at some configuration switches that was less addressed in the manual.
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