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Altera_Forum
Honored Contributor I
712 Views

synthesis question

Hi, 

I don't have access to synthesis tools at the moment and I am confused how this would synthesize:  

always @(posedge clk) 

if (rst) 

valid <= 0; 

else 

begin 

if (ften) 

valid <= 1; 

else if (ntas) 

valid <= 0; 

endThanks.
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3 Replies
Altera_Forum
Honored Contributor I
13 Views

 

--- Quote Start ---  

Hi, 

I don't have access to synthesis tools at the moment and I am confused how this would synthesize:  

always @(posedge clk) 

if (rst) 

valid <= 0; 

else 

begin 

if (ften) 

valid <= 1; 

else if (ntas) 

valid <= 0; 

endThanks. 

--- Quote End ---  

 

 

Hi, 

 

first of all you can download a Quartus Web edition from Altera for free. The web edition includes all you need. With some extensions your code could be synthesized. I have a small Quartus project for you atttached, in order to give you a starting point. 

 

 

 

Kind regards 

 

GPK
Altera_Forum
Honored Contributor I
13 Views

Thanks GPK. I plan to download the software. 

Can you post a text file of the gate netlist? 

 

Thanks again.
Altera_Forum
Honored Contributor I
13 Views

 

--- Quote Start ---  

Thanks GPK. I plan to download the software. 

Can you post a text file of the gate netlist? 

 

Thanks again. 

--- Quote End ---  

 

 

Hi, 

 

here is a netlist. 

 

Kind regards 

 

GPK 

 

// Copyright (C) 1991-2008 Altera Corporation 

// Your use of Altera Corporation's design tools, logic functions  

// and other software and tools, and its AMPP partner logic  

// functions, and any output files from any of the foregoing  

// (including device programming or simulation files), and any  

// associated documentation or information are expressly subject  

// to the terms and conditions of the Altera Program License  

// Subscription Agreement, Altera MegaCore Function License  

// Agreement, or other applicable license agreement, including,  

// without limitation, that your use is for the sole purpose of  

// programming logic devices manufactured by Altera and sold by  

// Altera or its authorized distributors. Please refer to the  

// applicable agreement for further details. 

 

// VENDOR "Altera" 

// PROGRAM "Quartus II" 

// VERSION "Version 8.1 Build 163 10/28/2008 SJ Full Version" 

 

// DATE "02/02/2009 11:38:54" 

 

module test ( 

rst, 

ften, 

ntas, 

clk, 

valid); 

input rst; 

input ften; 

input ntas; 

input clk; 

output valid; 

wire \valid~29 ; 

wire \valid~reg0 ; 

 

 

wire gnd; 

wire vcc; 

 

assign gnd = 1'b0; 

assign vcc = 1'b1; 

 

 

cycloneii_lcell_comb \valid~29_I ( 

.dataa(ften), 

.datab(ntas), 

.datac(\valid~reg0 ), 

.datad(rst), 

.combout(\valid~29 )); 

defparam \valid~29_I .sum_lutc_input = "datac"; 

defparam \valid~29_I .lut_mask = "00BA"; 

 

cycloneii_lcell_ff \valid~reg0_I ( 

.clk(clk), 

.datain(\valid~29 ), 

.regout(\valid~reg0 )); 

 

assign valid = \valid~reg0 ; 

 

endmodule
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