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Arria 10 GX development kit Pcie example design

Srini2
Beginner
1,098 Views

Hello sir/madam,

 

 I am working in ARRIA 10 GX development kit for testing the PCie end point protocol.I have configured the pcie end point IP for X1 lane and generated example design for that configured IP.

Given pin assignment and compiled the design with generated .SOF file.Programmed the .SOF file in development Board and detected the Pcie device ID in the host pc using RW everything tool.Detection is working fine.

 

My aim is to send the data from Pcie end point to root complex(host PC).For that I have taken the TX_ST_data,TX_ST_VALID in the signal tap analyser to see the data generated from the example design, but i didnt get any data from that signal. It is showing Zero in that signal.

 

Could anyone please share the working Pcie design which include data transfer from end point to Root complex(host PC)?

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wchiah
Employee
1,045 Views

Hi,


You can refer to example design below

https://www.rocketboards.org/foswiki/Projects/Arria10PCIeRootPortWithMSI


Regards,

Wincent_Intel


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wchiah
Employee
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Hi,

 

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

 

Regards,

Wincent_Intel


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wchiah
Employee
917 Views

Hi

 

We have not hear from you and this Case is idling. It is not recommended to idle for too long.

Therefore following our support policy, I have to put this case in close status. My apologies if any inconvenience cause

Hence, This thread will be transitioned to community support.

If you have a new question, feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread. Thank you

If you feel your support experience was less than a 9 or 10,

please allow me to correct it before closing or let me know the cause so that I may improve your future support experience.

 

Regards,

Wincent_Intel


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