As for the Async Reset for the flops - what polarity is preferable (posedge or negadge)?
If I don't define a default value for FF, will it be '0'?
Usually would be negedge
always @ (negedge <reset> or posedge <clock_signal>)
// Reset whenever the reset signal goes low, regardless of the clock
<register_variable> <= 1'b0;
// If not resetting, update the register output on the clock's rising edge
<register_variable> <= <data>;
You can right click the vhdl -> insert template -> verilog hdl-> logic -> register
Look into the details.
You can also look into https://www.intel.co.jp/content/dam/www/programmable/us/en/pdfs/literature/quartus2/qts_qii51006.pdf page 9-4
If you don't defined, there will be no reset port in your flop flop.