genvar i,j;
generate
for (i=0; i<=25; i=i+4) begin : generate_block_identifier // <-- example block name
mod16 f1 ( key_Qk_shift_i[i+3:i], new_salt_Or[i+3:i], input_data[i+3:i], r_out[i+3:i], xor_out[i+3:i], clk ,CurrentState);
for (j=0; j<=25; j=j+4) begin : generate_block_identifier_2
shift_mod shift ( key_Qk, CLK, currentState, j, key_Qk_shift_o);
end
end
endgenerate
key_Qk_shift_o is the output of the module
and key_Qk_shift_i is the input of the other module
this is how i am connecting them
wire [255:0] key_Qk_shift_i;
wire [255:0] key_Qk_shift_o;
tri [255:0] key_Qk_shift;
assign key_Qk_shift = key_Qk_shift_o;
assign key_Qk_shift_i = key_Qk_shift;
any help plz
