A BDF ( schematic is provided ) with some editing due to the sensitivity of the design, in addition to the report.
Also after compilation the report is not showing the registers used in this hierarchical design. this is the second time am facing this problem.
Thanks in advance
I cant provide the design file because it is very sensitive and classified work.
but, is there anything in mind for such a problem ?
Is there another way for helping instead the option of sending the design file ?
From the RTL Viewer,
Can you try to upgrade to Quartus Prime Standard version 18.1?
If the problem is not fixed, can you try to give me a simple test design file?
So that, I can duplicate the error as well.