HLS cosim error with acl_altera_syncram_wrapped.sv

[jmitrevs]

When I try to run cosim with "i++ -march=Arria10 <source files>" using Quartus Prime Pro 20.4 (or 20.3) on Cent OS 7, I get the following error:

# Model Technology ModelSim - Intel FPGA Edition vlog 2020.3 Compiler 2020.07 Jul 22 2020
# Start time: 17:18:44 on Feb 26,2021
# vlog -sv "+incdir+." ../../../components/mpl/mpl/mpl_internal_10/sim/acl_fifo.v -work mpl_internal_10 
# -- Compiling module acl_fifo
# 
# Top level modules:
# 	acl_fifo
# End time: 17:18:44 on Feb 26,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.3 Compiler 2020.07 Jul 22 2020
# Start time: 17:18:44 on Feb 26,2021
# vlog -sv "+incdir+." ../../../components/mpl/mpl/mpl_internal_10/sim/acl_altera_syncram_wrapped.sv -work mpl_internal_10 
# ** Error: ../../../components/mpl/mpl/mpl_internal_10/sim/acl_altera_syncram_wrapped.sv(92): Cannot open `include file "./acl_ecc.svh".
# -- Compiling module acl_altera_syncram_wrapped
# End time: 17:18:44 on Feb 26,2021, Elapsed time: 0:00:00
# Errors: 1, Warnings: 0

Do you know what is causing this and how I can fix it?

[MGRAV]

Any news about this ?

I have the same issue!

Mathieu

[VenkateshSathar]

can u run again with --debug-log and -ghdl option ? then attach the log and transcript with the post?

[jmitrevs]

Attached is the debug.log

[jmitrevs]

Additionally, here's a tar file of the HLS area. It can be compiled with:

cd policy_model/policy_prj_untrained_q204

i++ -march=Arria10 mpl_test.cpp firmware/mpl.cpp

(the mpl was a typo; should have been mlp, but I left it in to remain consistent).