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HLS with quartus-compile enabled failed using a library created from an RTL module using VHDL-2008


I have created a VHDL Entity with IEEE.FIXED_PKG and made a library from it to use it in HLS components. I can emulate the component and do also RTL simulation with it. But when I try to invoke the i++ compiler with --quartus-compile flag, the synthesis fails because in the generated QSF file is not the vhdl-2008 version enabled. The result is it cannot find the IEEE.FIXED_PKG library. It uses the standard vhdl-1993 verison. Is there a way to change to the vhdl-2008 version? Synthesis directive in the VHLD file does not help. Here is the command I use, using Qartus 20.4 Pro and also Quartus 21.2 Pro versions:

i++ -march=Arria10 libRTLMod.a --fpga-only -ghdl --quartus-compile -I ./lib -I./hdl test_comp_fpga_qii.o

HLS run Quartus compile failed


The debug.log files reports this:

Error (13785): VHDL Use Clause error at moving_avg.vhd(5): design library "ieee" does not contain primary unit "fixed_pkg" File: ...moving_avg.vhd Line: 5


In the test_comp_fpga_qii/quartus directory is a quartus_compile.qsf file. Here would help setting a global assignment like this:

set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008


Is there a way to guide the compiler to add such a line using the appropriate VHDL version?

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2 Replies

Hi @thj,


Thank you for posting in Intel community forum, hope all is well and apologies for the delayed in response.
If I understand the situation correctly, there are a way that you can set in the quartus to specify to the compiler on which VHDL version to use.


Please do look into the settings in the quartus project under Assignments -> Settings -> Compiler Settings -> VHDL Input
You would be able to chose the inputs there, please do let us know if that helps to clarify your doubts.


Best Wishes


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Hello BB,

Thank you for your answer.

At command line, I can invoke the i++ compiler with the compile flag --quartus-compile. That invokes the quartus synthesis tools (quartus compiler) with the fitter. The outcome of the fitter is important for me to estimate the resource consumption properly.

What I did is indeed to start the quartus project manually and changing the VHDL input to the correct version. Then I start the synthesis flow again. Now I investigate if the output is meaningful, because the i++ compile flow is broken, and I fear the quartus compile flow (fitter) optimizes away a lot because of not connected signals in the resulting hardware design.

By the way, I have instantiated an HDL object as described in the Intel High Level Synthesis Compiler Pro Edition Reference Manual Chapter 11.4. The reason is to investigate the resource consumption between a version written in HLS compared to one written in VHDL and the effect of the maximum throughput I can get when I insatiate the HDL object within my component function. For me the C++ (HLS, DPC++) features are very interesting, because that enables template metaprogramming as well and could be quite useful to create powerful designs with a minimum of resource consumption on FPGA hardware, too. 


Best Regards,


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