Hello, how can dataflow parallelism be implemented in Intel HLS in the STD edition without using the task mechanism (only available in the PRO edition)? A typical use case is shown here: https://youtu.be/aH1O4DZnjf8 Thanks, Thomas

[MEIYAN_L_Intel]

Hi, 

I had found out that the ihc::stream can only used in the Quartus Prime Pro edition based on the link below:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/hls/ug-hls-getting-started.pdf

I would like to suggest to used parallelize loops in Quartus Prime Standard Intel HLS to increase the parallel dataflow.

You can refer to user guide as link below with the subtitle "Parallelize Loops" which is placed at chapter 4.2:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/hls/ug-hls-best-practices.pdf

These methods can used reduce the latency as well.

Thanks.

[TMK]

Thank you for your reply. I think that you're proposing the solution to a different problem, unfortunately not the one addressed in the video. Could you please show how you would implement dataflow parallelism following your approach for the example from the video?

[HRZ]

>I would like to suggest to used parallelize loops in Quartus Prime Standard Intel HLS to increase the parallel dataflow.

Loop parallelization (i.e. unrolling) is completely different from dataflow parallelization. The former is for parallelizing iterations within one loop, the latter is for parallelizing multiple separate loop bodies with respect to each other; you cannot achieve the latter using the former. I am astonished that Intel is limiting certain features of the HLS compiler to the PRO version, preventing people who use older FPGAs only supported by the Standard version from being able to access them.

[MEIYAN_L_Intel]

Unfortunately, as per your mention certain features that can be used in Quartus Prime Pro edition only. This is due the developer are focusing more on Quartus Prime Pro edition compare to std.

[HRZ]

And what stops them from using the same version of the HLS compiler for both Quartus Standard and PRO, rather than creating one for the Standard version and another one for PRO? The HLS compiler just converts C/C++ code to HDL, it should not matter what the target FPGA or Quartus, is. Same applies to the OpenCL compiler. In fact, I am sure the same version of aoc was shipped with both the Standard version and the PRO version up to a certain point after which, for whatever reason, the developers started developing separate versions for each.

[TMK]

Thank you HRZ for raising this question. @MeiYanL_Intel​ , could you please let me know if and when we can expect new Intel HLS features in the Standard Edition. To my knowledge there hasn't been any release of the Quartus Prime Standard Edition this year yet. The longer this situation lasts, the harder it will be for Intel to motivate its customers to pay the maintenance/renewal fee for the Standard Edition. Why would you pay good money if you don't get any new features in return?

[TMK]

@MeiYanL_Intel​ Could you please share the plans regarding Intel HLS in the Standard Edition? Thank you.

[MEIYAN_L_Intel]

Hi,

There is no plan in enhancing features in Quartus Prime Standard Edition.

We are sorry to inform this.

Thanks.