Intel HLS (19.4) - Not supported device family except Stratix 10

[Pan]

I always used Arria10 device, when compiling with 19.3 version and everything worked as expected.

I shifted to 19.4 compiler recently, and since the shift, an error has been occurring when other devices, except Stratix10, are used. The error is transpiring even on designs successfully compiled with 19.3.

I attached two files - a log from the failed compilation (Arria10) and a part of a log from a successful compilation (Stratix 10).

I suppose it's another problem for developers, but isn't there any way to overcome it (besides using the Stratix 10 device)?

[MEIYAN_L_Intel]

Hi,

I had check the Arria 10 log file and I saw the information below:

Info: qsys-generate /home/local/xpanak04/p4base/compiler/p4hls/intel/tests/dummies/sys_launch_always_run/solution_4/intel_cosim.prj/components/foo/foo.ip --synthesis=VERILOG --output-directory=/home/local/xpanak04/p4base/compiler/p4hls/intel/tests/dummies/sys_launch_always_run/solution_4/intel_cosim.prj/components/foo/foo --family="Stratix 10" --part=Unknown

It seems like the qsys generated for Stratix 10 device but your selected device is Arria 10, hence there is a warning given that invalid device family name in input file: Arria 10.

Could you confirm the qsys-script: foo.tcl is selected the correct device?

Also, may I have the qsys-script: foo.tcl for further investigate?

Thanks

[Pan]

Hi,

I did not find the script in the compilation folder. Therefore I am providing you with the whole folder.

Thanks

[MEIYAN_L_Intel]

Hi,

May I know the design file for HLs compiler to compile?

Also, could you provide the command flow so that I can try it on my side for further investigate?

Thanks

[Pan]

Hi,

here you go. Just do make intel_sim and then make intel_cosim. The testbench outputs were fine before, but I altered the code a bit and had to reverse it back for you. Now, it doesn't show me testbench outputs for simulation. Even so, it doesn't effect platform designer fail in any way.

Also, I would like to point out that compilations are much slower then it used to be in 19.3.

Again, I am not unable to upload two files at once, so I zipped it.

Thanks for your time.

[MEIYAN_L_Intel]

Hi,

I had try to compile the design by using HLS compiler v19.3.

I had error shown while compiling the design and the error as below:

main.cpp:71:7: error: no member named 'launch_always_run' in namespace 'ihc'

    ihc::launch_always_run<my_task>();

    ~~~~~^

main.cpp:71:34: error: expected expression

    ihc::launch_always_run<my_task>();

Also, I had look into the design and you have mentioned there show an example from Intel as comment.

Could you direct me to the example provided by Intel or provide me the example name?

Thanks

[Pan]

Hi,

in this case, I provided, you can only test different devices. The ihc::launch_always_run is a new feature added in 19.4 compiler. Example found in the reference manual, section 13.13.

You can test anything you want. Platform Designer in 19.4 will always fail in case of Arria10 or another device except Stratix10.

I attach another example, that should work on 19.3 but doesn't work on 19.4. The device is set to Arria10.

Have a nice day.

[MEIYAN_L_Intel]

Hi, 

I had test the design code for "design" file and "example" file you uploaded. 

I could see the compilation for both files by HLS compiler v19.4 are successful by using the command make intel_sim and make intel_cosim. The results show in the attached file.

Also, I am able to run full compilation for the quartus_compile.qpf file as well.

May I know the information for foo_internal_inst file? This is because in the foo_generation.rpt file,it does not show the "foo_internal_inst" on my side. Also, I do not have this file in my directory.

Please let me know if I working in the wrong direction.

Thanks

[Pan]

Hi,

I will attach the compilation results of the last example I shared with you. When I looked into foo_generation.rpt, there is one difference at the start:

For 19.3 (solution_8):

Info: Starting: Create simulation model Info: qsys-generate /home/local/xpanak04/p4base/compiler/p4hls/intel/tutorials/1_possible_cpp_structure/solution_8/intel_cosim.prj/components/foo/foo.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/home/local/xpanak04/p4base/compiler/p4hls/intel/tutorials/1_possible_cpp_structure/solution_8/intel_cosim.prj/components/foo/foo --family="Arria 10" --part=10AX115U1F45I1SG

For 19.4 (solution_9):

Info: Starting: Create HDL design files for synthesis Info: qsys-generate /home/local/xpanak04/p4base/compiler/p4hls/intel/tutorials/1_possible_cpp_structure/solution_9/intel_cosim.prj/components/foo/foo.ip --synthesis=VERILOG --output-directory=/home/local/xpanak04/p4base/compiler/p4hls/intel/tutorials/1_possible_cpp_structure/solution_9/intel_cosim.prj/components/foo/foo --family="Stratix 10" --part=Unknown

The thing is - makefile is the same, code is the same, the enviroment set the same way and only compiler version is different. I don't know where foo_internal_inst comes from in case of 19.4. It just does. You will see 19.3 works with foo, not foo_internal_inst.

Thanks

[MEIYAN_L_Intel · Accepted solution]

Hi,

I am able to compile the example design in HLS compiler v19.3 and v19.4 and could not duplicate the error as shown on your side.

It seems like the problems is cause by the device files are not installed correctly. 

Could you try to reinstall the Arria 10 device files?

Thanks