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I'm asking if there is a way to simulate the generated RTL code fron an OpenCL design to debug the behavior ?
Thanks,
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Hi
If you have a use case , that would help. Since you can debug the OpenCL code itself to find and correct the issues.
Also you can use the emulation or simulation modes in the OpenCL SDK for FPGA.
But to be precise if you want to program the .aocx file and see the RTL created by the compiler for programming it in to FPGA, and simulate it, currently it wont be possible using the SDK.
Thanks and Regards
Anil

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