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Issue compiling code with volatile 3D array in loop

ymherklotz
Beginner
310 Views

Hi,

The following code seems to compile incorrectly in Intel i++ Lite 18.1 when targeting Cyclone V.

 

#include "HLS/hls.h"

static volatile int32_t a[9][1][7];

component int result() {
  int tmp = 1;
  for (int b = 0; b != 2; b++) {
    a[0][0][0] = 3;
    a[0][0][0] = a[0][0][0];
  }
  for (int i = 0; i < 9; i++)
    for (int k = 0; k < 7; k++)
      tmp ^= a[i][0][k];
  return tmp;
}

int main() {
  printf("%X\n", result());
}

 

The code above prints 0 when compiled with i++, however, it should return 2.  When compiling with the following command to generate the Verilog and simulating the design with Modelsim, intel i++ will return 0.

i++ test_Mod.cpp -v -march=CycloneV -o test-fpga

 

 

However, when compiling for x86 using the same command, the result is 2.

 

i++ test_Mod.cpp -march=x86-64 -o test-x86-64

 

This doesn't seem to occur with the i++ version that ships with the full version of Quartus, however, it might be because this i++ version somehow seems to unroll loops automatically (and incorrectly), whereas the full version of i++ doesn't seem to unroll the loops.

I noticed this because I get the following warnings:

Compiler Warning: Auto-unrolled loop at /home/ymherklotz/projects/hls_fuzzing/intel/intel/test_Mod.cpp:12
Compiler Warning: Auto-unrolled loop at /home/ymherklotz/projects/hls_fuzzing/intel/intel/test_Mod.cpp:7
0 Kudos
1 Reply
AnilErinch_A_Intel
259 Views

Hi ,

You can prevent loop automatic loop unrolling using #pragma unroll 0 and get he code working as expected.

Thanks and Regards

Anil


Reply