L- and H-tile Avalon Streaming Intel FPGA IP for PCI Express as a Root Port

[Shifali15]

Hi,
I want to use L- and H-tile Avalon Streaming Intel FPGA IP for PCI Express as a Root Port.
But i not able to understand formation of TLP packets and how to form the TLP header, so please suggest any example design.

Thanks

[Wincent_Altera]

Hi,

Thanks for reaching, 

• For PCIe Avalon ST L and H Tile Root Port procedure you may refer document at link below
• https://www.intel.com/content/www/us/en/docs/programmable/683111/21-1/root-port-enumeration.html
• TLP header information you may refer to same user guide as well
• https://www.intel.com/content/www/us/en/docs/programmable/683111/21-1/tlp-header-and-data-alignment-for-the.html

Hope this able to help, let me know if any further clarification is needed.

Regards,

Wincent_Intel

[Shifali15]

Thank you for your reply,

1. Is there any example designs available to understand the formation of these TLP headers?
2. I want to understand what are those pcie_hdr_byte0 , pcie_hdr_byte1..........pcie_hdr_byte15 is there any documents to explain these headers?

[Wincent_Altera]

Hi,

Apologize for late reply,

The pcie_hdr_byte0 , pcie_hdr_byte1 is Mapping Avalon-ST Packets to PCI Express TLPs

For detail , you can refer document below

https://www.intel.com/programmable/technical-pdfs/683111.pdf , Table 30.

Regards

Wincent_Intel

[Wincent_Altera]

Hi,

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

Regards,

Wincent_Intel

[Wincent_Altera]

Hi,

We do not receive any response from you to the previous answer that I provided.

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Regards,

Wincent_Intel