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L- and H-tile Avalon Streaming Intel FPGA IP for PCI Express as a Root Port

Shifali15
New Contributor I
995 Views

Hi,
I want to use L- and H-tile Avalon Streaming Intel FPGA IP for PCI Express as a Root Port.
But i not able to understand formation of TLP packets and how to form the TLP header, so please suggest any example design.

Thanks

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5 Replies
wchiah
Employee
962 Views

Hi,

 

Thanks for reaching, 

Hope this able to help, let me know if any further clarification is needed.

Regards,

Wincent_Intel

 


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Shifali15
New Contributor I
954 Views

Thank you for your reply,

  1. Is there any example designs available to understand the formation of these TLP headers?
  2. I want to understand what are those pcie_hdr_byte0 , pcie_hdr_byte1..........pcie_hdr_byte15 is there any documents to explain these headers?
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wchiah
Employee
907 Views

Hi,


Apologize for late reply,

The pcie_hdr_byte0 , pcie_hdr_byte1 is Mapping Avalon-ST Packets to PCI Express TLPs

For detail , you can refer document below

https://www.intel.com/programmable/technical-pdfs/683111.pdf , Table 30.


Regards

Wincent_Intel



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wchiah
Employee
879 Views

Hi,

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

Regards,

Wincent_Intel


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wchiah
Employee
873 Views

Hi,

 

We do not receive any response from you to the previous answer that I provided.

This thread will be transitioned to community support.

If you have a new question, feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread. Thank you

If you feel your support experience was less than a 9 or 10,

please allow me to correct it before closing or please let me know the cause so that I may improve your future support experience.

 

Regards,

Wincent_Intel


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