Regarding writing test bench for Intel OpenCL generated code.

[PVeli]

I donot have Mentor graphics Model SIm software with me. However I have Aldec Riviera pro tool.

Can you please help how to identify the DUT and procedure for writing test bench. Intel has given simulator support only to Mentor Graphics Model sim., using -march=simulator option where the host code is being drivern as Test bench.How to do that for other tools ?

[AnilErinch_A_Intel]

Possible duplicate of

https://community.intel.com/t5/Intel-High-Level-Design/OpenCL-RTL-simulation-using-ModelSim-Intel-FPGA-Edition-or-Aldec/td-p/1271480