Intel® High Level Design
Support for Intel® High Level Synthesis Compiler, DSP Builder, OneAPI for Intel® FPGAs, Intel® FPGA SDK for OpenCL™
663 Discussions

Regarding writing test bench for Intel OpenCL generated code.

PVeli
Beginner
‎05-02-2021 12:04 PM
575 Views

I donot have Mentor graphics Model SIm software with me. However I have Aldec Riviera pro tool.

Can you please help how to identify the DUT and procedure for writing test bench. Intel has given simulator support only to Mentor Graphics Model sim., using -march=simulator option where the host code is being drivern as Test bench.How to do that for other tools ?

0 Kudos

Link Copied

1 Reply
Reply

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.